From owner-freebsd-current@FreeBSD.ORG Fri Jun 16 21:00:30 2006 Return-Path: X-Original-To: freebsd-current@freebsd.org Delivered-To: freebsd-current@freebsd.org Received: from mx1.FreeBSD.org (mx1.freebsd.org [216.136.204.125]) by hub.freebsd.org (Postfix) with ESMTP id 4ABAC16A47D for ; Fri, 16 Jun 2006 21:00:30 +0000 (UTC) (envelope-from jhb@freebsd.org) Received: from server.baldwin.cx (66-23-211-162.clients.speedfactory.net [66.23.211.162]) by mx1.FreeBSD.org (Postfix) with ESMTP id 5362543D48 for ; Fri, 16 Jun 2006 21:00:29 +0000 (GMT) (envelope-from jhb@freebsd.org) Received: from localhost.corp.yahoo.com (john@localhost [127.0.0.1]) (authenticated bits=0) by server.baldwin.cx (8.13.4/8.13.4) with ESMTP id k5GL0Ndr061320; Fri, 16 Jun 2006 17:00:26 -0400 (EDT) (envelope-from jhb@freebsd.org) From: John Baldwin To: Andriy Gapon Date: Fri, 16 Jun 2006 15:09:28 -0400 User-Agent: KMail/1.9.1 References: <1148837064.00534930.1148826605@10.7.7.3> <200606011504.31635.jhb@freebsd.org> <44929864.4080207@icyb.net.ua> In-Reply-To: <44929864.4080207@icyb.net.ua> MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200606161509.28998.jhb@freebsd.org> X-Greylist: Sender succeeded SMTP AUTH authentication, not delayed by milter-greylist-2.0.2 (server.baldwin.cx [127.0.0.1]); Fri, 16 Jun 2006 17:00:27 -0400 (EDT) X-Virus-Scanned: ClamAV 0.87.1/1548/Fri Jun 16 13:53:47 2006 on server.baldwin.cx X-Virus-Status: Clean X-Spam-Status: No, score=-4.4 required=4.2 tests=ALL_TRUSTED,BAYES_00 autolearn=ham version=3.1.0 X-Spam-Checker-Version: SpamAssassin 3.1.0 (2005-09-13) on server.baldwin.cx Cc: freebsd-current@freebsd.org, Nate Lawson Subject: Re: Freeze due to performance_cx_lowest=LOW X-BeenThere: freebsd-current@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Discussions about the use of FreeBSD-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 16 Jun 2006 21:00:30 -0000 On Friday 16 June 2006 07:39, Andriy Gapon wrote: > on 01/06/2006 22:04 John Baldwin said the following: > > On Tuesday 30 May 2006 23:19, Nate Lawson wrote: > >> Andriy Gapon wrote: > >>> on 29/05/2006 23:10 Nate Lawson said the following: > >>>> disable apic (hint.apic.0.disabled="1"). I isolated this a little while > >>>> ago to the change to enable LAPIC timer. However, there is currently no > >>>> easy way to disable the LAPIC timer with APIC enabled so you have to > >>>> disable APIC. jhb@ and I have been discussing how to do this better but > >>>> no easy answers apparently. > >>> I am not sure what I am talking about, but is it potentially possible to > >>> drive timer system by more than one clock, actively using the most > >>> precise of them at any particular moment ? So that if LAPIC timer stops > >>> i8254 can be used instead. > >> That requires mixed mode delivery -- i8254 on legacy PIC irq and APIC > >> mode for other interrupts. jhb@ just killed this and isn't eager to add > >> it back. I'll let him explain if he has more to add. > > > > Namely that it is unreliable and expressly forbidden by the ACPI spec. > > > > Maybe I will say something too ignorant for this list, but is it > possible to drive hardclock with two interrupts (I haven't thought yet > how, though) and use RTC as the second interrupt source ? > I think that RTC/IRQ8 (usually) doesn't have problems associated with > 8254 timer/IRQ0 and can be used without mixed mode. Well, you could use the RTC instead of the lapic timer on CPU 0 and then use IPIs to forward clock interrupts to all the other CPUs just as we did before we used the lapic timer. -- John Baldwin