Date: Tue, 19 Aug 2003 16:21:38 -0700 (PDT) From: Joseph Davida <jd10008@yahoo.com> To: freebsd-questions@FreeBSD.ORG Subject: SMP synchronization Message-ID: <20030819232138.69420.qmail@web41410.mail.yahoo.com>
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Som question on FreeBSD 5.x SMP Synchronization: 1. On motherboards with 2-4 cpus (such as those from Intel and Supermicro and others), what is the cache-snooping chip part called? How can I determine if it is present or not? If the MP motherboard does not have hardware cache snooping, what does the FreeBSD kernel resort to? On old SMP HW architectures, a cross-processor interrupt was used to purge local cpu caches such that the issuing cpu would wait for all other cpu's to rendezvous to a known state, before the issuing cpu would proceed to try to lock the spin lock. All that, because of lack of cache snooping hardware. 2. Does FreeBSD employ priority inheritance to address priority inversion problems? 3. Is there a quantification of the current SMP granularity? I have more questions about the FreeBSD 5.x kernel, but will send them another time. Cheers, Joe __________________________________ Do you Yahoo!? Yahoo! SiteBuilder - Free, easy-to-use web site design software http://sitebuilder.yahoo.com
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