From owner-svn-src-head@freebsd.org Wed Sep 23 00:32:52 2020 Return-Path: Delivered-To: svn-src-head@mailman.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.nyi.freebsd.org (Postfix) with ESMTP id D59453E6C43; Wed, 23 Sep 2020 00:32:52 +0000 (UTC) (envelope-from bdragon@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 4BwzfX3YySz3yyS; Wed, 23 Sep 2020 00:32:51 +0000 (UTC) (envelope-from bdragon@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id C5D2827C78; Wed, 23 Sep 2020 00:32:50 +0000 (UTC) (envelope-from bdragon@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id 08N0WoMU035239; Wed, 23 Sep 2020 00:32:50 GMT (envelope-from bdragon@FreeBSD.org) Received: (from bdragon@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id 08N0Wok6035237; Wed, 23 Sep 2020 00:32:50 GMT (envelope-from bdragon@FreeBSD.org) Message-Id: <202009230032.08N0Wok6035237@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: bdragon set sender to bdragon@FreeBSD.org using -f From: Brandon Bergren Date: Wed, 23 Sep 2020 00:32:50 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r366041 - in head/sys/powerpc: include powernv X-SVN-Group: head X-SVN-Commit-Author: bdragon X-SVN-Commit-Paths: in head/sys/powerpc: include powernv X-SVN-Commit-Revision: 366041 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.33 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 23 Sep 2020 00:32:53 -0000 Author: bdragon Date: Wed Sep 23 00:32:50 2020 New Revision: 366041 URL: https://svnweb.freebsd.org/changeset/base/366041 Log: [PowerPC64LE] powernv ILE setup code. When running without a hypervisor, we need to set the ILE bit in the LPCR ourselves. For the boot processor, handle it in powernv_attach() like we do for other LPCR bits. No change for the APs, as they will use the lpcr global to set up their own LPCR when they do their own cpudep_ap_early_bootstrap() and pick up this automatically. Sponsored by: Tag1 Consulting, Inc. Modified: head/sys/powerpc/include/spr.h head/sys/powerpc/powernv/platform_powernv.c Modified: head/sys/powerpc/include/spr.h ============================================================================== --- head/sys/powerpc/include/spr.h Wed Sep 23 00:28:47 2020 (r366040) +++ head/sys/powerpc/include/spr.h Wed Sep 23 00:32:50 2020 (r366041) @@ -292,6 +292,7 @@ #define SPR_LPCR 0x13e /* .6. Logical Partitioning Control */ #define LPCR_LPES 0x008 /* Bit 60 */ #define LPCR_HVICE 0x002 /* Hypervisor Virtualization Interrupt (Arch 3.0) */ +#define LPCR_ILE (1ULL << 25) /* Interrupt Little-Endian (ISA 2.07) */ #define LPCR_UPRT (1ULL << 22) /* Use Process Table (ISA 3) */ #define LPCR_HR (1ULL << 20) /* Host Radix mode */ #define LPCR_PECE_DRBL (1ULL << 16) /* Directed Privileged Doorbell */ Modified: head/sys/powerpc/powernv/platform_powernv.c ============================================================================== --- head/sys/powerpc/powernv/platform_powernv.c Wed Sep 23 00:28:47 2020 (r366040) +++ head/sys/powerpc/powernv/platform_powernv.c Wed Sep 23 00:32:50 2020 (r366041) @@ -174,6 +174,10 @@ powernv_attach(platform_t plat) if (cpu_features2 & PPC_FEATURE2_ARCH_3_00) lpcr |= LPCR_HVICE; +#if BYTE_ORDER == LITTLE_ENDIAN + lpcr |= LPCR_ILE; +#endif + mtspr(SPR_LPCR, lpcr); isync();