From owner-freebsd-smp Wed Jul 16 15:45:36 1997 Return-Path: Received: (from root@localhost) by hub.freebsd.org (8.8.5/8.8.5) id PAA15257 for smp-outgoing; Wed, 16 Jul 1997 15:45:36 -0700 (PDT) Received: from ormail.intel.com (ormail.intel.com [134.134.248.3]) by hub.freebsd.org (8.8.5/8.8.5) with ESMTP id PAA15240; Wed, 16 Jul 1997 15:45:25 -0700 (PDT) Received: from ichips.intel.com (ichips.intel.com [134.134.50.200]) by ormail.intel.com (8.8.6/8.8.4) with ESMTP id PAA18838; Wed, 16 Jul 1997 15:44:43 -0700 (PDT) Received: from pdxlx008.intel.com by ichips.intel.com (8.7.4/jIII) id PAA29366; Wed, 16 Jul 1997 15:45:02 -0700 (PDT) Received: from pdxlx008 (localhost [127.0.0.1]) by pdxlx008.intel.com (8.8.6/8.7.3) with ESMTP id PAA07524; Wed, 16 Jul 1997 15:45:25 -0700 (PDT) Message-Id: <199707162245.PAA07524@pdxlx008.intel.com> To: Terry Lambert cc: smp@csn.net (Steve Passe), smp@FreeBSD.ORG, current@FreeBSD.ORG Subject: Re: self modifying kernel code In-reply-to: Your message of "Wed, 16 Jul 1997 14:41:26 PDT." <199707162141.OAA01599@phaeton.artisoft.com> Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Date: Wed, 16 Jul 1997 15:45:25 -0700 From: Wayne Scott Sender: owner-smp@FreeBSD.ORG X-Loop: FreeBSD.org Precedence: bulk > Are we assuming that the processors will be Pentium only? The icache > is not written back prior to the P5. This takes a significant number > of NOP's to flush the pipeline (as discussed in Van Guilluwe's "The > Undocumented PC" in the section where he investigates instruction cache > depth using self-modifying code). At startup the call is to a routine that computes the correct target address. In the fixup routine you change the call address and then jump to the target directly. It will be a long time before you actually execute the modified code. -Wayne Wayne Scott MD6 Architecture wscott@ichips.intel.com Work #: (503) 264-4165 Disclaimer: All views expressed are my own opinions, and not necessarily those of Intel Corporation.