Date: Mon, 13 Jan 1997 14:29:27 -0700 (MST) From: Terry Lambert <terry@lambert.org> To: imb@scgt.oz.au (michael butler) Cc: current@FreeBSD.ORG Subject: Re: multiple 2842 controllers Message-ID: <199701132129.OAA28285@phaeton.artisoft.com> In-Reply-To: <199701130732.SAA10914@asstdc.scgt.oz.au> from "michael butler" at Jan 13, 97 06:32:10 pm
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> I have an old 486DX/4 motherboard that I was trying to squeeze two Adaptec > 2842 controllers onto .. a small(-ish) news server. It has 3 VL slots but > they're documented as "J18 & J19 are master 0, J20 is master 1". Unless you can switch J18 or J19 to be master 1 as well, you can only have one bus mastering controller in this machine. The master value dictates whether a cache invalidation will be issued to the MMU following a bus mastering DMA. If you do not get a cache invalidation, then the cache will potentially contain bogus cached data lines for the memory region DMA'ed into. This was, incidently, the problem with the old Saturn I and Mercury I and Neptune I chipsets: they left the PCI DMA connect off the mask, so PCI bus masters would never invalidate the cache (ISA or EISA worked fine, however). A number of wholsalers are selling old P60 machines from Dell and Gateway -- beware: they have this problem. A hack fix is to BINVD the memory area for the data transfer in the driver; this will cause the cache lines to be flushed. A less hack fix for the busted hardware is to enable bouncing at all times, and to mark the bounce buffer pages non-cacheable. As long as you don't have an old Cyrix/TI processor using the TI chipmask (instead of the IBM "Blue Lightning" chipmask), this will work. If you have a Cyrix/TI processor using the TI chipmask, then the L1 cache will not honor the non-cacheable bit... in that case, you can only turn off the cache OR call BINVD on the buffer region when you get the "read request completed" in the driver. > I tried the controllers in J18 & J19 but the second one has all sorts of > bother, can't read IRQ correctly from EEPROM and selects 3.6 meg async for a > Quantum Atlas 4.3G .. not quite what I was after :-( > > I couldn't take the machine down for longer than ~15 mins so I thought I'd > ask here before making customers any more cranky .. do I have to have them > in J18 & J20 for this to work ? Unfortunately, this isn't a lot of time to work with. Have you tried disabling the L1 and L2 cache so that there is no need for "master 1" invalidation of cache contents? If this works, it would definitely point you to one of the above fixes for the problem. THen you should split L1/L2 to see if it is a problem with the slots not being master, or if it is a problem with the processor not obeying the cache line (Cyrix/TI processor -- if you turn off L1 and leave L2 on, this would confirm). Regards, Terry Lambert terry@lambert.org --- Any opinions in this posting are my own and not those of my present or previous employers.
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