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Sat, 4 Feb 2023 06:58:58 GMT (envelope-from git) Date: Sat, 4 Feb 2023 06:58:58 GMT Message-Id: <202302040658.3146ww5T008516@gitrepo.freebsd.org> To: ports-committers@FreeBSD.org, dev-commits-ports-all@FreeBSD.org, dev-commits-ports-main@FreeBSD.org From: Yuri Victorovich Subject: git: 0ad876d5fd2d - main - cad/py-cocotb: New port: Coroutine based cosimulation library for writing VHDL and Verilog List-Id: Commits to the main branch of the FreeBSD ports repository List-Archive: https://lists.freebsd.org/archives/dev-commits-ports-main List-Help: List-Post: List-Subscribe: List-Unsubscribe: Sender: owner-dev-commits-ports-main@freebsd.org X-BeenThere: dev-commits-ports-main@freebsd.org MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Git-Committer: yuri X-Git-Repository: ports X-Git-Refname: refs/heads/main X-Git-Reftype: branch X-Git-Commit: 0ad876d5fd2d1befbfa7f01ab6fa8f5279ff8ab1 Auto-Submitted: auto-generated X-ThisMailContainsUnwantedMimeParts: N The branch main has been updated by yuri: URL: https://cgit.FreeBSD.org/ports/commit/?id=0ad876d5fd2d1befbfa7f01ab6fa8f5279ff8ab1 commit 0ad876d5fd2d1befbfa7f01ab6fa8f5279ff8ab1 Author: Yuri Victorovich AuthorDate: 2023-02-04 06:58:11 +0000 Commit: Yuri Victorovich CommitDate: 2023-02-04 06:58:53 +0000 cad/py-cocotb: New port: Coroutine based cosimulation library for writing VHDL and Verilog --- cad/Makefile | 1 + cad/py-cocotb/Makefile | 40 ++++++++++++++++++++++++++++++++++++++++ cad/py-cocotb/distinfo | 3 +++ cad/py-cocotb/pkg-descr | 5 +++++ 4 files changed, 49 insertions(+) diff --git a/cad/Makefile b/cad/Makefile index fa412f520987..7d15ad17a9ab 100644 --- a/cad/Makefile +++ b/cad/Makefile @@ -102,6 +102,7 @@ SUBDIR += pcb-rnd SUBDIR += pdnmesh SUBDIR += py-cadquery + SUBDIR += py-cocotb SUBDIR += py-cq-editor SUBDIR += py-edalize SUBDIR += py-ezdxf diff --git a/cad/py-cocotb/Makefile b/cad/py-cocotb/Makefile new file mode 100644 index 000000000000..a2168ec07d4d --- /dev/null +++ b/cad/py-cocotb/Makefile @@ -0,0 +1,40 @@ +PORTNAME= cocotb +DISTVERSIONPREFIX= v +DISTVERSION= 1.7.2 +CATEGORIES= cad python +PKGNAMEPREFIX= ${PYTHON_PKGNAMEPREFIX} + +MAINTAINER= yuri@FreeBSD.org +COMMENT= Coroutine based cosimulation library for writing VHDL and Verilog +WWW= https://www.cocotb.org/ + +LICENSE= BSD3CLAUSE +LICENSE_FILE= ${WRKSRC}/LICENSE + +BUILD_DEPENDS= ${PYTHON_PKGNAMEPREFIX}wheel>0:devel/py-wheel@${PY_FLAVOR} +RUN_DEPENDS= ${PYTHON_PKGNAMEPREFIX}find-libpython>0:devel/py-find-libpython@${PY_FLAVOR} \ + gtkwave:cad/gtkwave + +USES= python:3.6+ +USE_PYTHON= pep517 autoplist pytest # https://github.com/cocotb/cocotb/issues/3230 +USE_GITHUB= yes + +TEST_ENV= ${MAKE_ENV} PYTHONPATH=${STAGEDIR}${PYTHONPREFIX_SITELIBDIR} +TEST_WRKSRC= ${WRKSRC}/tests + +OPTIONS_DEFINE= IVERILOG VERILATOR # GHDL - TODO +OPTIONS_DEFAULT= IVERILOG VERILATOR + +IVERILOG_DESC= Iverilog dependency +IVERILOG_RUN_DEPENDS= iverilog:cad/iverilog + +VERILATOR_DESC= Verilator dependency +VERILATOR_RUN_DEPENDS= verilator:cad/verilator + +post-install: + @${STRIP_CMD} \ + ${STAGEDIR}${PYTHON_SITELIBDIR}/cocotb/simulator${PYTHON_EXT_SUFFIX}.so \ + ${STAGEDIR}${PYTHON_SITELIBDIR}/cocotb/libs/lib*.so \ + ${STAGEDIR}${PYTHON_SITELIBDIR}/cocotb/libs/libcocotbvpi_icarus.vpl + +.include diff --git a/cad/py-cocotb/distinfo b/cad/py-cocotb/distinfo new file mode 100644 index 000000000000..f7f52cba0128 --- /dev/null +++ b/cad/py-cocotb/distinfo @@ -0,0 +1,3 @@ +TIMESTAMP = 1675490974 +SHA256 (cocotb-cocotb-v1.7.2_GH0.tar.gz) = 2b72f25e91a8733abc9a49171adcf67d04670eb64bdc6be0d8ee653ac6b1d69f +SIZE (cocotb-cocotb-v1.7.2_GH0.tar.gz) = 641521 diff --git a/cad/py-cocotb/pkg-descr b/cad/py-cocotb/pkg-descr new file mode 100644 index 000000000000..de72cfe264b0 --- /dev/null +++ b/cad/py-cocotb/pkg-descr @@ -0,0 +1,5 @@ +cocotb is an open source coroutine-based cosimulation testbench environment +for verifying VHDL and SystemVerilog RTL using Python. + +cocotb lets you verify chips like software: productive, simulator-agnostic, +in Python.