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Subject: Re: X2APIC support
To: Konstantin Belousov <kostikbel@gmail.com>
References: <20160912164412.GS34394@zxy.spb.ru>
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Cc: Slawa Olhovchenkov <slw@zxy.spb.ru>, stable@FreeBSD.org
From: Andriy Gapon <avg@FreeBSD.org>
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Date: Tue, 13 Sep 2016 18:52:19 +0300
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On 13/09/2016 18:22, Konstantin Belousov wrote:
> Any access
> to the LAPIC registers page in x2APIC mode faults.

Is this a fact?
I read the following in the specification:

  In x2APIC mode, the memory mapped interface is not available and any
  access to the MMIO interface will behave similar to that of a legacy xAPIC
  in globally disabled state.

But I couldn't find what actually happens for the legacy xAPIC in globally
disabled state.  For AMD processors it is documented that if xAPIC is disabled
then accessing the APIC memory range works the same as accessing the regular
memory.  That can be different for Intel processors, of course.

-- 
Andriy Gapon