From owner-svn-src-all@FreeBSD.ORG Thu Oct 27 21:27:37 2011 Return-Path: Delivered-To: svn-src-all@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id C1268106566B; Thu, 27 Oct 2011 21:27:37 +0000 (UTC) (envelope-from yongari@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:4f8:fff6::2c]) by mx1.freebsd.org (Postfix) with ESMTP id 97C9D8FC0A; Thu, 27 Oct 2011 21:27:37 +0000 (UTC) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.4/8.14.4) with ESMTP id p9RLRbOq026263; Thu, 27 Oct 2011 21:27:37 GMT (envelope-from yongari@svn.freebsd.org) Received: (from yongari@localhost) by svn.freebsd.org (8.14.4/8.14.4/Submit) id p9RLRbXv026260; Thu, 27 Oct 2011 21:27:37 GMT (envelope-from yongari@svn.freebsd.org) Message-Id: <201110272127.p9RLRbXv026260@svn.freebsd.org> From: Pyun YongHyeon Date: Thu, 27 Oct 2011 21:27:37 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Subject: svn commit: r226866 - head/sys/dev/bge X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 27 Oct 2011 21:27:37 -0000 Author: yongari Date: Thu Oct 27 21:27:37 2011 New Revision: 226866 URL: http://svn.freebsd.org/changeset/base/226866 Log: Rename hard-coded value 1 << 14 with BGE_RX_CPU_DRV_EVENT. This bit(SW event 7 in publicly available data sheet) is used to make RX CPU handle a firmware command and the bit is automatically cleared after RX CPU completed the command. Generally firmware command takes the following steps. 1. Write BGE_SRAM_FW_CMD_MB with a command. 2. Write BGE_SRAM_FW_CMD_LEN_MB with the length of the command in bytes. 3. Write BGE_SRAM_FW_CMD_DATA_MB with actual command data. 4. Generate BGE_RX_CPU_EVENT and let firmware handle the command. 5. Wait for the ACK of the firmware command. No functional changes. Modified: head/sys/dev/bge/if_bge.c head/sys/dev/bge/if_bgereg.h Modified: head/sys/dev/bge/if_bge.c ============================================================================== --- head/sys/dev/bge/if_bge.c Thu Oct 27 21:25:41 2011 (r226865) +++ head/sys/dev/bge/if_bge.c Thu Oct 27 21:27:37 2011 (r226866) @@ -1370,10 +1370,11 @@ bge_stop_fw(struct bge_softc *sc) if (sc->bge_asf_mode) { bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, BGE_FW_CMD_PAUSE); CSR_WRITE_4(sc, BGE_RX_CPU_EVENT, - CSR_READ_4(sc, BGE_RX_CPU_EVENT) | (1 << 14)); + CSR_READ_4(sc, BGE_RX_CPU_EVENT) | BGE_RX_CPU_DRV_EVENT); for (i = 0; i < 100; i++ ) { - if (!(CSR_READ_4(sc, BGE_RX_CPU_EVENT) & (1 << 14))) + if (!(CSR_READ_4(sc, BGE_RX_CPU_EVENT) & + BGE_RX_CPU_DRV_EVENT)) break; DELAY(10); } @@ -4111,7 +4112,8 @@ bge_asf_driver_up(struct bge_softc *sc) bge_writemem_ind(sc, BGE_SRAM_FW_CMD_LEN_MB, 4); bge_writemem_ind(sc, BGE_SRAM_FW_CMD_DATA_MB, 3); CSR_WRITE_4(sc, BGE_RX_CPU_EVENT, - CSR_READ_4(sc, BGE_RX_CPU_EVENT) | (1 << 14)); + CSR_READ_4(sc, BGE_RX_CPU_EVENT) | + BGE_RX_CPU_DRV_EVENT); } } } Modified: head/sys/dev/bge/if_bgereg.h ============================================================================== --- head/sys/dev/bge/if_bgereg.h Thu Oct 27 21:25:41 2011 (r226865) +++ head/sys/dev/bge/if_bgereg.h Thu Oct 27 21:27:37 2011 (r226866) @@ -1901,6 +1901,8 @@ #define BGE_EE_DELAY 0x6848 #define BGE_FASTBOOT_PC 0x6894 +#define BGE_RX_CPU_DRV_EVENT 0x00004000 + /* * NVRAM Control registers */