From owner-svn-src-all@FreeBSD.ORG Tue Jan 17 07:23:44 2012 Return-Path: Delivered-To: svn-src-all@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 52B5E106566C; Tue, 17 Jan 2012 07:23:44 +0000 (UTC) (envelope-from kib@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:4f8:fff6::2c]) by mx1.freebsd.org (Postfix) with ESMTP id 3DCD08FC14; Tue, 17 Jan 2012 07:23:44 +0000 (UTC) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.4/8.14.4) with ESMTP id q0H7Ni2Z073032; Tue, 17 Jan 2012 07:23:44 GMT (envelope-from kib@svn.freebsd.org) Received: (from kib@localhost) by svn.freebsd.org (8.14.4/8.14.4/Submit) id q0H7NiEJ073029; Tue, 17 Jan 2012 07:23:44 GMT (envelope-from kib@svn.freebsd.org) Message-Id: <201201170723.q0H7NiEJ073029@svn.freebsd.org> From: Konstantin Belousov Date: Tue, 17 Jan 2012 07:23:44 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Subject: svn commit: r230261 - in head/sys: amd64/include i386/include X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 17 Jan 2012 07:23:44 -0000 Author: kib Date: Tue Jan 17 07:23:43 2012 New Revision: 230261 URL: http://svn.freebsd.org/changeset/base/230261 Log: Add definitions related to XCR0. MFC after: 1 week Modified: head/sys/amd64/include/specialreg.h head/sys/i386/include/specialreg.h Modified: head/sys/amd64/include/specialreg.h ============================================================================== --- head/sys/amd64/include/specialreg.h Tue Jan 17 07:21:23 2012 (r230260) +++ head/sys/amd64/include/specialreg.h Tue Jan 17 07:23:43 2012 (r230261) @@ -66,6 +66,7 @@ #define CR4_PCE 0x00000100 /* Performance monitoring counter enable */ #define CR4_FXSR 0x00000200 /* Fast FPU save/restore used by OS */ #define CR4_XMM 0x00000400 /* enable SIMD/MMX2 to use except 16 */ +#define CR4_XSAVE 0x00040000 /* XSETBV/XGETBV */ /* * Bits in AMD64 special registers. EFER is 64 bits wide. @@ -76,6 +77,18 @@ #define EFER_NXE 0x000000800 /* PTE No-Execute bit enable (R/W) */ /* + * Intel Extended Features registers + */ +#define XCR0 0 /* XFEATURE_ENABLED_MASK register */ + +#define XFEATURE_ENABLED_X87 0x00000001 +#define XFEATURE_ENABLED_SSE 0x00000002 +#define XFEATURE_ENABLED_AVX 0x00000004 + +#define XFEATURE_AVX \ + (XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE | XFEATURE_ENABLED_AVX) + +/* * CPUID instruction features register */ #define CPUID_FPU 0x00000001 Modified: head/sys/i386/include/specialreg.h ============================================================================== --- head/sys/i386/include/specialreg.h Tue Jan 17 07:21:23 2012 (r230260) +++ head/sys/i386/include/specialreg.h Tue Jan 17 07:23:43 2012 (r230261) @@ -66,6 +66,7 @@ #define CR4_PCE 0x00000100 /* Performance monitoring counter enable */ #define CR4_FXSR 0x00000200 /* Fast FPU save/restore used by OS */ #define CR4_XMM 0x00000400 /* enable SIMD/MMX2 to use except 16 */ +#define CR4_XSAVE 0x00040000 /* XSETBV/XGETBV */ /* * Bits in AMD64 special registers. EFER is 64 bits wide.