From owner-freebsd-mips@FreeBSD.ORG Thu Jan 30 03:51:57 2014 Return-Path: Delivered-To: freebsd-mips@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTPS id D721DA6D; Thu, 30 Jan 2014 03:51:57 +0000 (UTC) Received: from cdptpa-omtalb.mail.rr.com (cdptpa-omtalb.mail.rr.com [75.180.132.120]) by mx1.freebsd.org (Postfix) with ESMTP id 70BCA1D82; Thu, 30 Jan 2014 03:51:57 +0000 (UTC) X-Authority-Analysis: v=2.0 cv=H69ZMpki c=1 sm=0 a=Hbpc8ax9VmIgqBixU/K2CA==:17 a=dBRESv0yCI8A:10 a=ozSPa0bqj5AA:10 a=8nJEP1OIZ-IA:10 a=6I5d2MoRAAAA:8 a=KGjhK52YXX0A:10 a=vpU8xItVDkoA:10 a=E31hHOKmAAAA:8 a=I8Tm2jY7AAAA:8 a=3F8ov1ys2yz_GBS30kIA:9 a=wPNLvfGTeEIA:10 a=SV7veod9ZcQA:10 a=vXOQVunnJF4A:10 a=Hbpc8ax9VmIgqBixU/K2CA==:117 X-Cloudmark-Score: 0 X-Authenticated-User: X-Originating-IP: 76.187.139.93 Received: from [76.187.139.93] ([76.187.139.93:50474] helo=[192.168.0.2]) by cdptpa-oedge04.mail.rr.com (envelope-from ) (ecelerity 2.2.3.46 r()) with ESMTP id AA/B1-11872-B5CC9E25; Thu, 30 Jan 2014 03:51:55 +0000 Content-Type: text/plain; charset=iso-8859-1 Mime-Version: 1.0 (Mac OS X Mail 6.6 \(1510\)) Subject: Re: More trapframe panics From: Stacey Son In-Reply-To: Date: Wed, 29 Jan 2014 21:51:56 -0600 Content-Transfer-Encoding: quoted-printable Message-Id: References: <52E42A1B.3040907@rewt.org.uk> <6354182D-B1D3-4B2E-BEEC-37A2A725A099@bsdimp.com> <52E67F45.20402@rewt.org.uk> <2912AEFA-AA0C-456A-A814-363478BFC900@bsdimp.com> <52E781C6.2050308@rewt.org.uk> To: Adrian Chadd X-Mailer: Apple Mail (2.1510) Cc: "freebsd-mips@freebsd.org" X-BeenThere: freebsd-mips@freebsd.org X-Mailman-Version: 2.1.17 Precedence: list List-Id: Porting FreeBSD to MIPS List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 30 Jan 2014 03:51:57 -0000 On Jan 29, 2014, at 4:29 PM, Adrian Chadd wrote: > isn't there a way to probe the valid pagemask values? >=20 > I thought I read some way of writing in pagemask values into a fixed > TLB entry and then reading them back to see which bit(s) are set and > cleared. >=20 > That way we could maybe do the above at boot-time with minimal = evilness. Yes, see page 107 of http://www.t-es-t.hu/download/mips/md00090c.pdf "Software may determine which page sizes are supported by writing all = ones to the PageMask register, then reading the value back. If a pair of = bits reads back as ones, the processor implements that page size. The = operation of the pro- cessor is UNDEFINED if software loads the Mask = field with a value other than one of those listed in Table 9.16, even if = the hardware returns a different value on read. Hardware may depend on = this requirement in implementing hard- ware structures" -stacey.=