From owner-svn-src-all@FreeBSD.ORG Thu Nov 26 14:56:59 2009 Return-Path: Delivered-To: svn-src-all@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 9A7171065696; Thu, 26 Nov 2009 14:56:59 +0000 (UTC) (envelope-from mav@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:4f8:fff6::2c]) by mx1.freebsd.org (Postfix) with ESMTP id 6E1DF8FC1C; Thu, 26 Nov 2009 14:56:59 +0000 (UTC) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.3/8.14.3) with ESMTP id nAQEuxfB085180; Thu, 26 Nov 2009 14:56:59 GMT (envelope-from mav@svn.freebsd.org) Received: (from mav@localhost) by svn.freebsd.org (8.14.3/8.14.3/Submit) id nAQEuxA5085178; Thu, 26 Nov 2009 14:56:59 GMT (envelope-from mav@svn.freebsd.org) Message-Id: <200911261456.nAQEuxA5085178@svn.freebsd.org> From: Alexander Motin Date: Thu, 26 Nov 2009 14:56:59 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-8@freebsd.org X-SVN-Group: stable-8 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Subject: svn commit: r199833 - stable/8/sys/dev/ata/chipsets X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 26 Nov 2009 14:56:59 -0000 Author: mav Date: Thu Nov 26 14:56:58 2009 New Revision: 199833 URL: http://svn.freebsd.org/changeset/base/199833 Log: MFC r199645, r199646: Fix Intel PATA UDMA timings setting, affecting write performance. Binary divider value 10 specified in datasheet is not a hex 0x10. UDMA2 should be 33/2 instead of 66/4, which is documented as reverved, UDMA4 should be 66/2 instead of 66/4, which is definitely wrong. Release over-agressive WDMA0 mode timings as close to spec as chip can. Modified: stable/8/sys/dev/ata/chipsets/ata-intel.c Directory Properties: stable/8/sys/ (props changed) stable/8/sys/amd64/include/xen/ (props changed) stable/8/sys/cddl/contrib/opensolaris/ (props changed) stable/8/sys/contrib/dev/acpica/ (props changed) stable/8/sys/contrib/pf/ (props changed) stable/8/sys/dev/xen/xenpci/ (props changed) Modified: stable/8/sys/dev/ata/chipsets/ata-intel.c ============================================================================== --- stable/8/sys/dev/ata/chipsets/ata-intel.c Thu Nov 26 14:52:14 2009 (r199832) +++ stable/8/sys/dev/ata/chipsets/ata-intel.c Thu Nov 26 14:56:58 2009 (r199833) @@ -301,7 +301,7 @@ ata_intel_new_setmode(device_t dev, int u_int32_t mask40 = 0, new40 = 0; u_int8_t mask44 = 0, new44 = 0; int error; - u_int8_t timings[] = { 0x00, 0x00, 0x10, 0x21, 0x23, 0x10, 0x21, 0x23, + u_int8_t timings[] = { 0x00, 0x00, 0x10, 0x21, 0x23, 0x00, 0x21, 0x23, 0x23, 0x23, 0x23, 0x23, 0x23, 0x23 }; mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma); @@ -319,7 +319,7 @@ ata_intel_new_setmode(device_t dev, int ata_mode2str(mode), ctlr->chip->text); if (!error) { if (mode >= ATA_UDMA0) { - u_int8_t utimings[] = { 0x00, 0x01, 0x10, 0x01, 0x10, 0x01, 0x10 }; + u_int8_t utimings[] = { 0x00, 0x01, 0x02, 0x01, 0x02, 0x01, 0x02 }; pci_write_config(gparent, 0x48, reg48 | (0x0001 << devno), 2); pci_write_config(gparent, 0x4a, @@ -331,7 +331,7 @@ ata_intel_new_setmode(device_t dev, int pci_write_config(gparent, 0x4a, (reg4a & ~(0x3 << (devno << 2))),2); } reg54 |= 0x0400; - if (mode >= ATA_UDMA2) + if (mode >= ATA_UDMA3) reg54 |= (0x1 << devno); else reg54 &= ~(0x1 << devno);