From owner-svn-src-head@freebsd.org Wed Nov 28 06:54:51 2018 Return-Path: Delivered-To: svn-src-head@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 37EB0114A0F0; Wed, 28 Nov 2018 06:54:51 +0000 (UTC) (envelope-from arybchik@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id CE00483725; Wed, 28 Nov 2018 06:54:50 +0000 (UTC) (envelope-from arybchik@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 52FF126C3F; Wed, 28 Nov 2018 06:54:50 +0000 (UTC) (envelope-from arybchik@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id wAS6so0Q084125; Wed, 28 Nov 2018 06:54:50 GMT (envelope-from arybchik@FreeBSD.org) Received: (from arybchik@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id wAS6sn5U084120; Wed, 28 Nov 2018 06:54:49 GMT (envelope-from arybchik@FreeBSD.org) Message-Id: <201811280654.wAS6sn5U084120@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: arybchik set sender to arybchik@FreeBSD.org using -f From: Andrew Rybchenko Date: Wed, 28 Nov 2018 06:54:49 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r341111 - head/sys/dev/sfxge/common X-SVN-Group: head X-SVN-Commit-Author: arybchik X-SVN-Commit-Paths: head/sys/dev/sfxge/common X-SVN-Commit-Revision: 341111 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Rspamd-Queue-Id: CE00483725 X-Spamd-Result: default: False [1.21 / 15.00]; local_wl_from(0.00)[FreeBSD.org]; NEURAL_SPAM_LONG(0.55)[0.554,0]; NEURAL_SPAM_MEDIUM(0.42)[0.424,0]; ASN(0.00)[asn:11403, ipnet:2610:1c1:1::/48, country:US]; NEURAL_SPAM_SHORT(0.23)[0.229,0] X-Rspamd-Server: mx1.freebsd.org X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 28 Nov 2018 06:54:51 -0000 Author: arybchik Date: Wed Nov 28 06:54:49 2018 New Revision: 341111 URL: https://svnweb.freebsd.org/changeset/base/341111 Log: sfxge(4): move legacy board config to ef10 NIC board cfg Submitted by: Andy Moreton Sponsored by: Solarflare Communications, Inc. Differential Revision: https://reviews.freebsd.org/D18187 Modified: head/sys/dev/sfxge/common/ef10_nic.c head/sys/dev/sfxge/common/hunt_nic.c head/sys/dev/sfxge/common/medford2_nic.c (contents, props changed) head/sys/dev/sfxge/common/medford_nic.c Modified: head/sys/dev/sfxge/common/ef10_nic.c ============================================================================== --- head/sys/dev/sfxge/common/ef10_nic.c Wed Nov 28 06:54:37 2018 (r341110) +++ head/sys/dev/sfxge/common/ef10_nic.c Wed Nov 28 06:54:49 2018 (r341111) @@ -1575,6 +1575,7 @@ ef10_nic_board_cfg( const efx_nic_ops_t *enop = enp->en_enop; efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip); efx_nic_cfg_t *encp = &(enp->en_nic_cfg); + uint32_t board_type = 0; uint32_t port; uint32_t pf; uint32_t vf; @@ -1632,13 +1633,28 @@ ef10_nic_board_cfg( EFX_MAC_ADDR_COPY(encp->enc_mac_addr, mac_addr); + /* Board configuration (legacy) */ + rc = efx_mcdi_get_board_cfg(enp, &board_type, NULL, NULL); + if (rc != 0) { + /* Unprivileged functions may not be able to read board cfg */ + if (rc == EACCES) + board_type = 0; + else + goto fail5; + } + + encp->enc_board_type = board_type; + encp->enc_clk_mult = 1; /* not used for EF10 */ + /* Get remaining controller-specific board config */ if ((rc = enop->eno_board_cfg(enp)) != 0) if (rc != EACCES) - goto fail5; + goto fail6; return (0); +fail6: + EFSYS_PROBE(fail6); fail5: EFSYS_PROBE(fail5); fail4: Modified: head/sys/dev/sfxge/common/hunt_nic.c ============================================================================== --- head/sys/dev/sfxge/common/hunt_nic.c Wed Nov 28 06:54:37 2018 (r341110) +++ head/sys/dev/sfxge/common/hunt_nic.c Wed Nov 28 06:54:49 2018 (r341111) @@ -104,7 +104,6 @@ hunt_board_cfg( __in efx_nic_t *enp) { efx_nic_cfg_t *encp = &(enp->en_nic_cfg); - uint32_t board_type = 0; ef10_link_state_t els; efx_port_t *epp = &(enp->en_port); uint32_t mask; @@ -124,26 +123,13 @@ hunt_board_cfg( EFX_STATIC_ASSERT(1U << EFX_VI_WINDOW_SHIFT_8K == 8192); encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_8K; - /* Board configuration */ - rc = efx_mcdi_get_board_cfg(enp, &board_type, NULL, NULL); - if (rc != 0) { - /* Unprivileged functions may not be able to read board cfg */ - if (rc == EACCES) - board_type = 0; - else - goto fail1; - } - - encp->enc_board_type = board_type; - encp->enc_clk_mult = 1; /* not used for Huntington */ - /* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */ if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0) - goto fail2; + goto fail1; /* Obtain the default PHY advertised capabilities */ if ((rc = ef10_phy_get_link(enp, &els)) != 0) - goto fail3; + goto fail2; epp->ep_default_adv_cap_mask = els.els_adv_cap_mask; epp->ep_adv_cap_mask = els.els_adv_cap_mask; @@ -174,7 +160,7 @@ hunt_board_cfg( else if ((rc == ENOTSUP) || (rc == ENOENT)) encp->enc_bug35388_workaround = B_FALSE; else - goto fail4; + goto fail3; /* * If the bug41750 workaround is enabled, then do not test interrupts, @@ -193,7 +179,7 @@ hunt_board_cfg( } else if ((rc == ENOTSUP) || (rc == ENOENT)) { encp->enc_bug41750_workaround = B_FALSE; } else { - goto fail5; + goto fail4; } if (EFX_PCI_FUNCTION_IS_VF(encp)) { /* Interrupt testing does not work for VFs. See bug50084. */ @@ -231,12 +217,12 @@ hunt_board_cfg( } else if ((rc == ENOTSUP) || (rc == ENOENT)) { encp->enc_bug26807_workaround = B_FALSE; } else { - goto fail6; + goto fail5; } /* Get clock frequencies (in MHz). */ if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0) - goto fail7; + goto fail6; /* * The Huntington timer quantum is 1536 sysclk cycles, documented for @@ -255,7 +241,7 @@ hunt_board_cfg( /* Check capabilities of running datapath firmware */ if ((rc = ef10_get_datapath_caps(enp)) != 0) - goto fail8; + goto fail7; /* Alignment for receive packet DMA buffers */ encp->enc_rx_buf_align_start = 1; @@ -305,13 +291,13 @@ hunt_board_cfg( * can result in time-of-check/time-of-use bugs. */ if ((rc = ef10_get_privilege_mask(enp, &mask)) != 0) - goto fail9; + goto fail8; encp->enc_privilege_mask = mask; /* Get interrupt vector limits */ if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) { if (EFX_PCI_FUNCTION_IS_PF(encp)) - goto fail10; + goto fail9; /* Ignore error (cannot query vector limits from a VF). */ base = 0; @@ -327,7 +313,7 @@ hunt_board_cfg( encp->enc_tx_tso_tcp_header_offset_limit = EF10_TCP_HEADER_OFFSET_LIMIT; if ((rc = hunt_nic_get_required_pcie_bandwidth(enp, &bandwidth)) != 0) - goto fail11; + goto fail10; encp->enc_required_pcie_bandwidth_mbps = bandwidth; /* All Huntington devices have a PCIe Gen3, 8 lane connector */ @@ -335,8 +321,6 @@ hunt_board_cfg( return (0); -fail11: - EFSYS_PROBE(fail11); fail10: EFSYS_PROBE(fail10); fail9: Modified: head/sys/dev/sfxge/common/medford2_nic.c ============================================================================== --- head/sys/dev/sfxge/common/medford2_nic.c Wed Nov 28 06:54:37 2018 (r341110) +++ head/sys/dev/sfxge/common/medford2_nic.c Wed Nov 28 06:54:49 2018 (r341111) @@ -78,7 +78,6 @@ medford2_board_cfg( __in efx_nic_t *enp) { efx_nic_cfg_t *encp = &(enp->en_nic_cfg); - uint32_t board_type = 0; ef10_link_state_t els; efx_port_t *epp = &(enp->en_port); uint32_t mask; @@ -102,26 +101,13 @@ medford2_board_cfg( encp->enc_vi_window_shift = vi_window_shift; - /* Board configuration */ - rc = efx_mcdi_get_board_cfg(enp, &board_type, NULL, NULL); - if (rc != 0) { - /* Unprivileged functions may not be able to read board cfg */ - if (rc == EACCES) - board_type = 0; - else - goto fail2; - } - - encp->enc_board_type = board_type; - encp->enc_clk_mult = 1; /* not used for Medford2 */ - /* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */ if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0) - goto fail3; + goto fail2; /* Obtain the default PHY advertised capabilities */ if ((rc = ef10_phy_get_link(enp, &els)) != 0) - goto fail4; + goto fail3; epp->ep_default_adv_cap_mask = els.els_adv_cap_mask; epp->ep_adv_cap_mask = els.els_adv_cap_mask; @@ -165,11 +151,11 @@ medford2_board_cfg( else if ((rc == ENOTSUP) || (rc == ENOENT)) encp->enc_bug61265_workaround = B_FALSE; else - goto fail5; + goto fail4; /* Get clock frequencies (in MHz). */ if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0) - goto fail6; + goto fail5; /* * The Medford2 timer quantum is 1536 dpcpu_clk cycles, documented for @@ -181,7 +167,7 @@ medford2_board_cfg( /* Check capabilities of running datapath firmware */ if ((rc = ef10_get_datapath_caps(enp)) != 0) - goto fail7; + goto fail6; /* Alignment for receive packet DMA buffers */ encp->enc_rx_buf_align_start = 1; @@ -189,7 +175,7 @@ medford2_board_cfg( /* Get the RX DMA end padding alignment configuration */ if ((rc = efx_mcdi_get_rxdp_config(enp, &end_padding)) != 0) { if (rc != EACCES) - goto fail8; + goto fail7; /* Assume largest tail padding size supported by hardware */ end_padding = 256; @@ -241,13 +227,13 @@ medford2_board_cfg( * can result in time-of-check/time-of-use bugs. */ if ((rc = ef10_get_privilege_mask(enp, &mask)) != 0) - goto fail9; + goto fail8; encp->enc_privilege_mask = mask; /* Get interrupt vector limits */ if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) { if (EFX_PCI_FUNCTION_IS_PF(encp)) - goto fail10; + goto fail9; /* Ignore error (cannot query vector limits from a VF). */ base = 0; @@ -270,14 +256,12 @@ medford2_board_cfg( rc = medford2_nic_get_required_pcie_bandwidth(enp, &bandwidth); if (rc != 0) - goto fail11; + goto fail10; encp->enc_required_pcie_bandwidth_mbps = bandwidth; encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN3; return (0); -fail11: - EFSYS_PROBE(fail11); fail10: EFSYS_PROBE(fail10); fail9: Modified: head/sys/dev/sfxge/common/medford_nic.c ============================================================================== --- head/sys/dev/sfxge/common/medford_nic.c Wed Nov 28 06:54:37 2018 (r341110) +++ head/sys/dev/sfxge/common/medford_nic.c Wed Nov 28 06:54:49 2018 (r341111) @@ -74,7 +74,6 @@ medford_board_cfg( __in efx_nic_t *enp) { efx_nic_cfg_t *encp = &(enp->en_nic_cfg); - uint32_t board_type = 0; ef10_link_state_t els; efx_port_t *epp = &(enp->en_port); uint32_t mask; @@ -99,26 +98,13 @@ medford_board_cfg( EFX_STATIC_ASSERT(1U << EFX_VI_WINDOW_SHIFT_8K == 8192); encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_8K; - /* Board configuration */ - rc = efx_mcdi_get_board_cfg(enp, &board_type, NULL, NULL); - if (rc != 0) { - /* Unprivileged functions may not be able to read board cfg */ - if (rc == EACCES) - board_type = 0; - else - goto fail1; - } - - encp->enc_board_type = board_type; - encp->enc_clk_mult = 1; /* not used for Medford */ - /* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */ if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0) - goto fail2; + goto fail1; /* Obtain the default PHY advertised capabilities */ if ((rc = ef10_phy_get_link(enp, &els)) != 0) - goto fail3; + goto fail2; epp->ep_default_adv_cap_mask = els.els_adv_cap_mask; epp->ep_adv_cap_mask = els.els_adv_cap_mask; @@ -162,11 +148,11 @@ medford_board_cfg( else if ((rc == ENOTSUP) || (rc == ENOENT)) encp->enc_bug61265_workaround = B_FALSE; else - goto fail4; + goto fail3; /* Get clock frequencies (in MHz). */ if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0) - goto fail5; + goto fail4; /* * The Medford timer quantum is 1536 dpcpu_clk cycles, documented for @@ -178,7 +164,7 @@ medford_board_cfg( /* Check capabilities of running datapath firmware */ if ((rc = ef10_get_datapath_caps(enp)) != 0) - goto fail6; + goto fail5; /* Alignment for receive packet DMA buffers */ encp->enc_rx_buf_align_start = 1; @@ -186,7 +172,7 @@ medford_board_cfg( /* Get the RX DMA end padding alignment configuration */ if ((rc = efx_mcdi_get_rxdp_config(enp, &end_padding)) != 0) { if (rc != EACCES) - goto fail7; + goto fail6; /* Assume largest tail padding size supported by hardware */ end_padding = 256; @@ -238,13 +224,13 @@ medford_board_cfg( * can result in time-of-check/time-of-use bugs. */ if ((rc = ef10_get_privilege_mask(enp, &mask)) != 0) - goto fail8; + goto fail7; encp->enc_privilege_mask = mask; /* Get interrupt vector limits */ if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) { if (EFX_PCI_FUNCTION_IS_PF(encp)) - goto fail9; + goto fail8; /* Ignore error (cannot query vector limits from a VF). */ base = 0; @@ -267,14 +253,12 @@ medford_board_cfg( rc = medford_nic_get_required_pcie_bandwidth(enp, &bandwidth); if (rc != 0) - goto fail10; + goto fail9; encp->enc_required_pcie_bandwidth_mbps = bandwidth; encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN3; return (0); -fail10: - EFSYS_PROBE(fail10); fail9: EFSYS_PROBE(fail9); fail8: