Date: Tue, 17 Apr 2018 21:00:52 +0000 From: bugzilla-noreply@freebsd.org To: ports-bugs@FreeBSD.org Subject: [Bug 227591] [NEW PORT] devel/yosys - Verilog RTL syntensis Message-ID: <bug-227591-7788@https.bugs.freebsd.org/bugzilla/>
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https://bugs.freebsd.org/bugzilla/show_bug.cgi?id=3D227591 Bug ID: 227591 Summary: [NEW PORT] devel/yosys - Verilog RTL syntensis Product: Ports & Packages Version: Latest Hardware: Any OS: Any Status: New Severity: Affects Only Me Priority: --- Component: Individual Port(s) Assignee: ports-bugs@FreeBSD.org Reporter: propaliidealist@gmail.com Created attachment 192600 --> https://bugs.freebsd.org/bugzilla/attachment.cgi?id=3D192600&action= =3Dedit svn diff of the port Yosys is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains. WWW: http://www.clifford.at/yosys/ portlint: looks fine poudriere testport: ok --=20 You are receiving this mail because: You are the assignee for the bug.=
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