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Date:      Wed, 30 Oct 2024 01:02:17 GMT
From:      Kevin Bowling <kbowling@FreeBSD.org>
To:        src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-branches@FreeBSD.org
Subject:   git: 86efff54916b - stable/14 - ixv: Check cap return before MSI-X enable write
Message-ID:  <202410300102.49U12HPP023076@gitrepo.freebsd.org>

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The branch stable/14 has been updated by kbowling:

URL: https://cgit.FreeBSD.org/src/commit/?id=86efff54916bba7b7543699fe5922d8363f16c11

commit 86efff54916bba7b7543699fe5922d8363f16c11
Author:     Jeremiah Lott <jlott@averesystems.com>
AuthorDate: 2024-10-27 07:18:54 +0000
Commit:     Kevin Bowling <kbowling@FreeBSD.org>
CommitDate: 2024-10-30 01:01:04 +0000

    ixv: Check cap return before MSI-X enable write
    
    In the QEMU workaround code in if_ixv.c, the ixv driver calls
    pci_find_cap(dev, PCIY_MSIX, &rid). It is not checking the return code
    from that function and the function appears to always be failing. This
    then causes the driver to use the rid variable uninitialized, which
    will mean setting a bit at an arbitrary offset in pci config space. For
    now, this seems to have no adverse impact, but it could easily cause
    very subtle problems.
    
    PR:             207037
    Sponsored by:   BBOX.io
    
    (cherry picked from commit b87b3696c973ef0a9df70143cd89f6b488531e93)
---
 sys/dev/ixgbe/if_ixv.c | 13 ++++++++-----
 1 file changed, 8 insertions(+), 5 deletions(-)

diff --git a/sys/dev/ixgbe/if_ixv.c b/sys/dev/ixgbe/if_ixv.c
index 467a56e7269f..58384af5eea7 100644
--- a/sys/dev/ixgbe/if_ixv.c
+++ b/sys/dev/ixgbe/if_ixv.c
@@ -1073,11 +1073,14 @@ ixv_if_msix_intr_assign(if_ctx_t ctx, int msix)
 	 */
 	if (sc->hw.mac.type == ixgbe_mac_82599_vf) {
 		int msix_ctrl;
-		pci_find_cap(dev, PCIY_MSIX, &rid);
-		rid += PCIR_MSIX_CTRL;
-		msix_ctrl = pci_read_config(dev, rid, 2);
-		msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE;
-		pci_write_config(dev, rid, msix_ctrl, 2);
+		if (pci_find_cap(dev, PCIY_MSIX, &rid)) {
+			device_printf(dev, "Finding MSIX capability failed\n");
+		} else {
+			rid += PCIR_MSIX_CTRL;
+			msix_ctrl = pci_read_config(dev, rid, 2);
+			msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE;
+			pci_write_config(dev, rid, msix_ctrl, 2);
+		}
 	}
 
 	return (0);



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