From owner-svn-src-all@freebsd.org Tue Dec 3 19:18:34 2019 Return-Path: Delivered-To: svn-src-all@mailman.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.nyi.freebsd.org (Postfix) with ESMTP id 167391BA45B; Tue, 3 Dec 2019 19:18:34 +0000 (UTC) (envelope-from manu@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) server-signature RSA-PSS (4096 bits) client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 47SBbY6rPLz3LkL; Tue, 3 Dec 2019 19:18:33 +0000 (UTC) (envelope-from manu@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id C8ECD1C567; Tue, 3 Dec 2019 19:18:33 +0000 (UTC) (envelope-from manu@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id xB3JIXiX079462; Tue, 3 Dec 2019 19:18:33 GMT (envelope-from manu@FreeBSD.org) Received: (from manu@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id xB3JIXcJ079459; Tue, 3 Dec 2019 19:18:33 GMT (envelope-from manu@FreeBSD.org) Message-Id: <201912031918.xB3JIXcJ079459@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: manu set sender to manu@FreeBSD.org using -f From: Emmanuel Vadot Date: Tue, 3 Dec 2019 19:18:33 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r355356 - head/sys/arm64/rockchip/clk X-SVN-Group: head X-SVN-Commit-Author: manu X-SVN-Commit-Paths: head/sys/arm64/rockchip/clk X-SVN-Commit-Revision: 355356 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 03 Dec 2019 19:18:34 -0000 Author: manu Date: Tue Dec 3 19:18:32 2019 New Revision: 355356 URL: https://svnweb.freebsd.org/changeset/base/355356 Log: arm64: rockchip: rl3399: Remove the ability to put the PLL in normal mode at boot RK3399 PLLs have three modes : - Normal, where they behave normally and their freq is calculated based on the registers values. - Slow, where the PLL freq is 24Mhz (well, the external oscillator). - Deep Slow, used for suspend where the freq is 32Khz. We used to put every CPU related PLL in normal mode but it can cause problem if the firmware didn't setup the clocks register correctly. And even if it did but left the pll in slow or deep slow mode that might be because the PMIC suppling voltage for the CPU haven't been configured yet and we cannot do that at this point. So remove the ability to set PLLs to normal mode at boot to avoid any problems. Modified: head/sys/arm64/rockchip/clk/rk3399_cru.c head/sys/arm64/rockchip/clk/rk_clk_pll.c head/sys/arm64/rockchip/clk/rk_clk_pll.h Modified: head/sys/arm64/rockchip/clk/rk3399_cru.c ============================================================================== --- head/sys/arm64/rockchip/clk/rk3399_cru.c Tue Dec 3 19:14:02 2019 (r355355) +++ head/sys/arm64/rockchip/clk/rk3399_cru.c Tue Dec 3 19:18:32 2019 (r355356) @@ -692,7 +692,7 @@ static struct rk_clk_armclk_rates rk3399_cpu_b_rates[] /* Standard PLL. */ -#define PLL(_id, _name, _base, _nm) \ +#define PLL(_id, _name, _base) \ { \ .type = RK3399_CLK_PLL, \ .clk.pll = &(struct rk_clk_pll_def) { \ @@ -703,7 +703,6 @@ static struct rk_clk_armclk_rates rk3399_cpu_b_rates[] .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ .base_offset = _base, \ .rates = rk3399_pll_rates, \ - .normal_mode = _nm \ }, \ } @@ -796,13 +795,13 @@ static struct rk_clk rk3399_clks[] = { FFACT(0, "clk_ddrc_div2", "clk_ddrc", 1, 2), /* PLLs */ - PLL(PLL_APLLL, "lpll", 0x00, false), - PLL(PLL_APLLB, "bpll", 0x20, true), - PLL(PLL_DPLL, "dpll", 0x40, false), - PLL(PLL_CPLL, "cpll", 0x60, false), - PLL(PLL_GPLL, "gpll", 0x80, false), - PLL(PLL_NPLL, "npll", 0xA0, false), - PLL(PLL_VPLL, "vpll", 0xC0, false), + PLL(PLL_APLLL, "lpll", 0x00), + PLL(PLL_APLLB, "bpll", 0x20), + PLL(PLL_DPLL, "dpll", 0x40), + PLL(PLL_CPLL, "cpll", 0x60), + PLL(PLL_GPLL, "gpll", 0x80), + PLL(PLL_NPLL, "npll", 0xA0), + PLL(PLL_VPLL, "vpll", 0xC0), /* CRU_CLKSEL_CON0 */ CDIV(0, "aclkm_core_l_c", "armclkl", 0, Modified: head/sys/arm64/rockchip/clk/rk_clk_pll.c ============================================================================== --- head/sys/arm64/rockchip/clk/rk_clk_pll.c Tue Dec 3 19:14:02 2019 (r355355) +++ head/sys/arm64/rockchip/clk/rk_clk_pll.c Tue Dec 3 19:18:32 2019 (r355356) @@ -54,8 +54,6 @@ struct rk_clk_pll_sc { struct rk_clk_pll_rate *rates; struct rk_clk_pll_rate *frac_rates; - - bool normal_mode; }; #define WRITE4(_clk, off, val) \ @@ -346,18 +344,8 @@ static int rk3399_clk_pll_init(struct clknode *clk, device_t dev) { struct rk_clk_pll_sc *sc; - uint32_t reg; sc = clknode_get_softc(clk); - - if (sc->normal_mode) { - /* Setting to normal mode */ - reg = RK3399_CLK_PLL_MODE_NORMAL << RK3399_CLK_PLL_MODE_SHIFT; - reg |= RK3399_CLK_PLL_MODE_MASK << RK_CLK_PLL_MASK_SHIFT; - WRITE4(clk, sc->base_offset + RK3399_CLK_PLL_MODE_OFFSET, - reg | RK3399_CLK_PLL_WRITE_MASK); - } - clknode_init_parent_idx(clk, 0); return (0); @@ -549,7 +537,6 @@ rk3399_clk_pll_register(struct clkdom *clkdom, struct sc->flags = clkdef->flags; sc->rates = clkdef->rates; sc->frac_rates = clkdef->frac_rates; - sc->normal_mode = clkdef->normal_mode; clknode_register(clkdom, clk); Modified: head/sys/arm64/rockchip/clk/rk_clk_pll.h ============================================================================== --- head/sys/arm64/rockchip/clk/rk_clk_pll.h Tue Dec 3 19:14:02 2019 (r355355) +++ head/sys/arm64/rockchip/clk/rk_clk_pll.h Tue Dec 3 19:18:32 2019 (r355356) @@ -57,8 +57,6 @@ struct rk_clk_pll_def { struct rk_clk_pll_rate *rates; struct rk_clk_pll_rate *frac_rates; - - bool normal_mode; }; #define RK_CLK_PLL_HAVE_GATE 0x1