From owner-freebsd-bugs@FreeBSD.ORG Thu Jul 17 10:10:03 2008 Return-Path: Delivered-To: freebsd-bugs@hub.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 9745E1065670 for ; Thu, 17 Jul 2008 10:10:03 +0000 (UTC) (envelope-from gnats@FreeBSD.org) Received: from freefall.freebsd.org (freefall.freebsd.org [IPv6:2001:4f8:fff6::28]) by mx1.freebsd.org (Postfix) with ESMTP id 882ED8FC16 for ; Thu, 17 Jul 2008 10:10:03 +0000 (UTC) (envelope-from gnats@FreeBSD.org) Received: from freefall.freebsd.org (gnats@localhost [127.0.0.1]) by freefall.freebsd.org (8.14.2/8.14.2) with ESMTP id m6HAA3h7081458 for ; Thu, 17 Jul 2008 10:10:03 GMT (envelope-from gnats@freefall.freebsd.org) Received: (from gnats@localhost) by freefall.freebsd.org (8.14.2/8.14.1/Submit) id m6HAA3rN081457; Thu, 17 Jul 2008 10:10:03 GMT (envelope-from gnats) Date: Thu, 17 Jul 2008 10:10:03 GMT Message-Id: <200807171010.m6HAA3rN081457@freefall.freebsd.org> To: freebsd-bugs@FreeBSD.org From: Luoqi Chen Cc: Subject: Re: kern/118842: [apic] Boot failure with apic enabled (FreeBSD 7) X-BeenThere: freebsd-bugs@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list Reply-To: Luoqi Chen List-Id: Bug reports List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 17 Jul 2008 10:10:03 -0000 The following reply was made to PR kern/118842; it has been noted by GNATS. From: Luoqi Chen To: "bug-followup@FreeBSD.org" , "dragonsa@highveldmail.co.za" , "jhb@freebsd.org" Cc: Subject: Re: kern/118842: [apic] Boot failure with apic enabled (FreeBSD 7) Date: Thu, 17 Jul 2008 02:44:00 -0700 I've identified the cause: the SATA device in nForce chipset has the HyperT= ransport MSI mapping capability, and we unconditionally enable the MSI->HT = mapping even though we don't use MSI in our ATA driver, this likely confuse= d the device. John, it is unclear to me why we enable the MSI->HT mapping at all given th= at we always allocate MSI addresses from local APIC. To utilize HT interrup= t mechanism, shouldn't we be programming MSI with addresses from the HT MSI= mapping capability register (the device's or that of a parent bridge)? For those who are having the same problem, please try commenting out the MS= I mapping enabling code and see if it works for you, Index: pci.c =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D RCS file: /home/ncvs/src/sys/dev/pci/pci.c,v retrieving revision 1.355.2.2 diff -u -r1.355.2.2 pci.c --- pci.c 12 Feb 2008 20:20:56 -0000 1.355.2.2 +++ pci.c 17 Jul 2008 09:36:12 -0000 @@ -564,9 +564,11 @@ (long long)addr); } +#if 0 /* Enable MSI -> HT mapping. */ val |=3D PCIM_HTCMD_MSI_ENABLE; WREG(ptr + PCIR_HT_COMMAND, val, 2); +#endif break; } break; Thanks -lq