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From: Greg V To: freebsd-arm@freebsd.org, Michael Tuexen , Dmitry Skorodumov Subject: Re: gic-v2 and SGI interrupts on boot CPU In-Reply-To: <2B7A227B-245F-4F1B-A700-263C3FE56B68@freebsd.org> References: <2B7A227B-245F-4F1B-A700-263C3FE56B68@freebsd.org> Message-ID: <13A8B0FE-6300-4980-8DA9-49C7A37840CC@unrelenting.technology> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT X-Migadu-Auth-User: greg@unrelenting.technology X-Rspamd-Queue-Id: 4FQ1tT3SFXz3vgk X-Spamd-Bar: --- Authentication-Results: mx1.freebsd.org; dkim=pass header.d=unrelenting.technology header.s=key1 header.b=SbwS1Hvg; dmarc=pass (policy=none) header.from=unrelenting.technology; spf=pass (mx1.freebsd.org: domain of greg@unrelenting.technology designates 2001:41d0:2:267:: as permitted sender) smtp.mailfrom=greg@unrelenting.technology X-Spamd-Result: default: False [-4.00 / 15.00]; ARC_NA(0.00)[]; NEURAL_HAM_MEDIUM(-1.00)[-1.000]; R_DKIM_ALLOW(-0.20)[unrelenting.technology:s=key1]; FROM_HAS_DN(0.00)[]; RCPT_COUNT_THREE(0.00)[3]; TO_DN_SOME(0.00)[]; R_SPF_ALLOW(-0.20)[+ip6:2001:41d0:2:267::]; MIME_GOOD(-0.10)[text/plain]; NEURAL_HAM_LONG(-1.00)[-1.000]; SPAMHAUS_ZRD(0.00)[2001:41d0:2:267:::from:127.0.2.255]; TO_MATCH_ENVRCPT_SOME(0.00)[]; DKIM_TRACE(0.00)[unrelenting.technology:+]; DMARC_POLICY_ALLOW(-0.50)[unrelenting.technology,none]; NEURAL_HAM_SHORT(-1.00)[-0.996]; RCVD_COUNT_ZERO(0.00)[0]; FROM_EQ_ENVFROM(0.00)[]; MIME_TRACE(0.00)[0:+]; RBL_DBL_DONT_QUERY_IPS(0.00)[2001:41d0:2:267:::from]; ASN(0.00)[asn:16276, ipnet:2001:41d0::/32, country:FR]; MID_RHS_MATCH_FROM(0.00)[]; MAILMAN_DEST(0.00)[freebsd-arm] X-BeenThere: freebsd-arm@freebsd.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Porting FreeBSD to ARM processors List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 21 Apr 2021 00:40:35 -0000 On April 20, 2021 10:38:44 PM UTC, Michael Tuexen w= rote: >> On 21=2E Apr 2021, at 00:02, Dmitry Skorodumov via freebsd-arm wrote: >>=20 >> Hi >>=20 >>=20 >> It looks like code for gic-v2 in FreeBSD not quite correctly relies on = implementation defined behaviour of GIC=2E >>=20 >> The gic 2=2E0 spec https://developer=2Earm=2Ecom/documentation/i= hi0048/bb chapter 3=2E2=2E2 "Interrupt controls in the GIC" states the foll= owing: >>=20 >> "Whether SGIs are permanently enabled, or can be enabled and disabled b= y writes to the GICD_ISENABLERn and GICD_ICENABLERn, is IMPLEMENTATION DEFI= NED=2E" >>=20 >> But code in sys/arm/arm/gic=2Ec assumes that SGI are always enabled and= doesn't configure them at initialization=2E They are initialized only for = secondary CPUs - in arm_gic_init_secondary()=2E >>=20 >> For sure it is a rather minor issue, since all appears to be ok in gic-= v3 (v3 code enables SGIs for all CPUs, including the boot one)=2E And even = if platform supports only gic-v2, likely SGIs are always enabled anyway=2E = So, my post is rather pedantic notice without real life case=2E >Dear all, > >if I understand things correctly, the problem described is the cause whic= h does not >allow to use more than one CPU core in FreeBSD when running on Parallels = Desktop on >an M1 based Mac=2E It runs perfectly well with one core, but with multipl= e cores it >locks up during boot=2E Hmm if I'm reading it correctly, the gicv2 driver *does* do this on second= ary CPUs, just not on the boot one=2E Which doesn't sound like something th= at would cause SMP boot to break but single-core to still work=2E Seems like people using QEMU with Hypervisor=2Eframework patches do have S= MP working fine: https://gist=2Egithub=2Ecom/ctsrc/a1f57933a2cde9abc0f07be12889f97f so go b= other Parallels about their bugs ;)