From owner-svn-src-head@freebsd.org Sun Nov 26 14:28:28 2017 Return-Path: Delivered-To: svn-src-head@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id CF5BDDE75A5; Sun, 26 Nov 2017 14:28:28 +0000 (UTC) (envelope-from ed@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 8BD5C6C313; Sun, 26 Nov 2017 14:28:28 +0000 (UTC) (envelope-from ed@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id vAQESRgE073127; Sun, 26 Nov 2017 14:28:27 GMT (envelope-from ed@FreeBSD.org) Received: (from ed@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id vAQESRxo073124; Sun, 26 Nov 2017 14:28:27 GMT (envelope-from ed@FreeBSD.org) Message-Id: <201711261428.vAQESRxo073124@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: ed set sender to ed@FreeBSD.org using -f From: Ed Schouten Date: Sun, 26 Nov 2017 14:28:27 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r326227 - in head/sys/arm64: arm64 include X-SVN-Group: head X-SVN-Commit-Author: ed X-SVN-Commit-Paths: in head/sys/arm64: arm64 include X-SVN-Commit-Revision: 326227 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.25 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 26 Nov 2017 14:28:28 -0000 Author: ed Date: Sun Nov 26 14:28:27 2017 New Revision: 326227 URL: https://svnweb.freebsd.org/changeset/base/326227 Log: Make 32-bit system calls end up in svc_handler(). The nice thing about ARM64 is that it's pretty elegant to install separate trap/exception handlers for 32-bit and 64-bit processes. That said, for all other architectures (e.g., i386 on amd64) we always let 32-bit counterparts go through the regular system call codepath. Let's do the same on ARM64. Reviewed by: andrew Differential Revision: https://reviews.freebsd.org/D13146 Modified: head/sys/arm64/arm64/exception.S head/sys/arm64/arm64/trap.c head/sys/arm64/include/armreg.h Modified: head/sys/arm64/arm64/exception.S ============================================================================== --- head/sys/arm64/arm64/exception.S Sun Nov 26 10:02:43 2017 (r326226) +++ head/sys/arm64/arm64/exception.S Sun Nov 26 14:28:27 2017 (r326227) @@ -219,8 +219,8 @@ exception_vectors: vempty /* FIQ 64-bit EL0 */ vector el0_error /* Error 64-bit EL0 */ - vempty /* Synchronous 32-bit EL0 */ - vempty /* IRQ 32-bit EL0 */ + vector el0_sync /* Synchronous 32-bit EL0 */ + vector el0_irq /* IRQ 32-bit EL0 */ vempty /* FIQ 32-bit EL0 */ - vempty /* Error 32-bit EL0 */ + vector el0_error /* Error 32-bit EL0 */ Modified: head/sys/arm64/arm64/trap.c ============================================================================== --- head/sys/arm64/arm64/trap.c Sun Nov 26 10:02:43 2017 (r326226) +++ head/sys/arm64/arm64/trap.c Sun Nov 26 14:28:27 2017 (r326227) @@ -381,7 +381,8 @@ do_el0_sync(struct thread *td, struct trapframe *frame panic("VFP exception in userland"); #endif break; - case EXCP_SVC: + case EXCP_SVC32: + case EXCP_SVC64: svc_handler(td, frame); break; case EXCP_INSN_ABORT_L: Modified: head/sys/arm64/include/armreg.h ============================================================================== --- head/sys/arm64/include/armreg.h Sun Nov 26 10:02:43 2017 (r326226) +++ head/sys/arm64/include/armreg.h Sun Nov 26 14:28:27 2017 (r326227) @@ -123,7 +123,8 @@ #define EXCP_UNKNOWN 0x00 /* Unkwn exception */ #define EXCP_FP_SIMD 0x07 /* VFP/SIMD trap */ #define EXCP_ILL_STATE 0x0e /* Illegal execution state */ -#define EXCP_SVC 0x15 /* SVC trap */ +#define EXCP_SVC32 0x11 /* SVC trap for AArch32 */ +#define EXCP_SVC64 0x15 /* SVC trap for AArch64 */ #define EXCP_MSR 0x18 /* MSR/MRS trap */ #define EXCP_INSN_ABORT_L 0x20 /* Instruction abort, from lower EL */ #define EXCP_INSN_ABORT 0x21 /* Instruction abort, from same EL */