From owner-freebsd-hardware@FreeBSD.ORG Thu Nov 13 19:47:01 2008 Return-Path: Delivered-To: freebsd-hardware@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 3F5571065677; Thu, 13 Nov 2008 19:47:01 +0000 (UTC) (envelope-from jhb@freebsd.org) Received: from server.baldwin.cx (bigknife-pt.tunnel.tserv9.chi1.ipv6.he.net [IPv6:2001:470:1f10:75::2]) by mx1.freebsd.org (Postfix) with ESMTP id D47808FC1B; Thu, 13 Nov 2008 19:47:00 +0000 (UTC) (envelope-from jhb@freebsd.org) Received: from localhost.corp.yahoo.com (john@localhost [IPv6:::1]) (authenticated bits=0) by server.baldwin.cx (8.14.3/8.14.3) with ESMTP id mADJkO2r096236; Thu, 13 Nov 2008 14:46:54 -0500 (EST) (envelope-from jhb@freebsd.org) From: John Baldwin To: freebsd-hardware@freebsd.org Date: Thu, 13 Nov 2008 14:38:25 -0500 User-Agent: KMail/1.9.7 References: <704830.24415.qm@web45815.mail.sp1.yahoo.com> <366483.43588.qm@web45807.mail.sp1.yahoo.com> <20081113081936.GA14779@icarus.home.lan> In-Reply-To: <20081113081936.GA14779@icarus.home.lan> MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200811131438.25904.jhb@freebsd.org> X-Greylist: Sender succeeded SMTP AUTH authentication, not delayed by milter-greylist-2.0.2 (server.baldwin.cx [IPv6:::1]); Thu, 13 Nov 2008 14:46:55 -0500 (EST) X-Virus-Scanned: ClamAV 0.93.1/8628/Thu Nov 13 10:57:02 2008 on server.baldwin.cx X-Virus-Status: Clean X-Spam-Status: No, score=-2.6 required=4.2 tests=AWL,BAYES_00,NO_RELAYS autolearn=ham version=3.1.3 X-Spam-Checker-Version: SpamAssassin 3.1.3 (2006-06-01) on server.baldwin.cx Cc: Jeremy Chadwick , Won De Erick Subject: Re: IRQ31 and IRQ32 on HPDL585 running FreeBSD 7.0 are consuming HIGH CPU usage X-BeenThere: freebsd-hardware@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: General discussion of FreeBSD hardware List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 13 Nov 2008 19:47:01 -0000 On Thursday 13 November 2008 03:19:36 am Jeremy Chadwick wrote: > On Thu, Nov 13, 2008 at 12:07:37AM -0800, Won De Erick wrote: > > Noted on this, I will update you through this thread. > > > > However is there any possibility of the following: > > > > > I don't know if there's a way to split the interrupt request for each bce's Rx and Tx, > > > which means a total of four IRQs, and eventually four cores (or 4 CPUs) > > > for the transactions. With this way, the IDLE processors would be utilized. > > > > What I mean here is, for the two interfaces: > > > > one IRQ for bce0 Rx > > one IRQ for bce0 Tx > > one IRQ for bce1 Rx > > one IRQ for bce1 Tx > > I can't even begin to imagine how this would be possible on any NIC. igb(4) does it. It is quite possible and one of the purposes of MSI. However, the current bce(4) hardware does not support this. It only allows for a single message and thus a single IRQ per-device. -- John Baldwin