Date: Fri, 18 Feb 2000 19:44:22 -0800 From: Arun Sharma <adsharma@c62443-a.frmt1.sfba.home.com> To: freebsd-hackers@freebsd.org Subject: Re: 64bit OS? Message-ID: <200002190344.TAA18841@c62443-a.frmt1.sfba.home.com> In-Reply-To: <200002190110.MAA31421@mycenae.ilion.eu.org> References: <200002190110.MAA31421@mycenae.ilion.eu.org>
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On Sat, 19 Feb 2000 12:10:14 +1100, Patryk Zadarnowski <patrykz@ilion.eu.org> wrote: > > Kevin Elphinstone did a PhD thesis on TLB structures for 64 bit address spaces > and it turns out that hash tables perform quite poorly. I'd suggest GPTs > instead, or maybe LPCtrie that Chris Szmajda has been working on here at UNSW. > Both have the advantage of supporting multiple page sizes that IA64 (and > Alpha) offer, and hence dramatically increasing the TLB coverage over what > Linux (or any other commercial OS that took a bite at IA64) can achieve. > Kevin's paper's at: > ftp://ftp.cse.unsw.edu.au/pub/users/disy/papers/Elphinstone:phd.ps.gz Thanks for the great pointer. IA-64 short format = Linear virtual arrays described in this paper. Long format = conventional hashed page table. Page 116 on LVAs in the paper talks about the disadvantages of using the short format: (a) Increased TLB misses (b) Memory overhead similar to multilevel page tables I don't know if clustered page tables can be implemented with the hardware support present in IA-64. More investigation is needed. > Maybe that way we can somehow make use of the Itanium's 4GB page size ;)))) The best thing is the abilitity to have large pinned TLB entries - they're called TRs (translation registers) in the manuals. Linux for example maps all of kernel memory with one huge TR. This also accomplishes the traditional Linux way of mapping all of physical memory into kernel virtual. -Arun To Unsubscribe: send mail to majordomo@FreeBSD.org with "unsubscribe freebsd-hackers" in the body of the message
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