Date: Thu, 09 Aug 2001 03:58:01 +0900 From: Mitsuru IWASAKI <iwasaki@jp.FreeBSD.org> To: arch@FreeBSD.ORG Cc: audit@FreeBSD.ORG, kumabu@t3.rim.or.jp Subject: CFR: Timing to enable CR4.PGE bit Message-ID: <20010809035801V.iwasaki@jp.FreeBSD.org>
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Hi, I've found a report in Japanese mailing list that CR4.PGE seems to be enabled before CR0.PG in locore.s. This was originally reported by Kumabuchi-san (Thanks!). According to developer's manual from Intel site, ftp://download.intel.com/design/PentiumII/manuals/24319202.pdf ---- 2.5. CONTROL REGISTERS [snip] PGE (2-17) Page Global Enable (bit 7 of CR4). (Introduced in the P6 family processors.) Enables the global page feature when set; disables the global page feature when clear. [snip] In addition, the bit must not ^^^^^^^^^^^^^^^^ be enabled before paging is enabled via CR0.PG. Program correctness ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ may be affected by reversing this sequence, and processor performance will be impacted. ---- Currently, we enable CR4.PGE bit in create_pagetables, then enable CR0.PG in locore.s. This seems to violate Intel's note. I've made patches for this, moving CR4.PGE enabling code to just before calling init386(). Index: locore.s =================================================================== RCS file: /home/ncvs/src/sys/i386/i386/locore.s,v retrieving revision 1.144 diff -u -r1.144 locore.s --- locore.s 2001/07/12 06:32:50 1.144 +++ locore.s 2001/08/08 17:49:28 @@ -374,6 +374,12 @@ movl IdlePTD,%esi movl %esi,PCB_CR3(%eax) + testl $CPUID_PGE, R(cpu_feature) + jz 1f + movl %cr4, %eax + orl $CR4_PGE, %eax + movl %eax, %cr4 +1: pushl physfree /* value of first for init386(first) */ call init386 /* wire 386 chip for unix operation */ @@ -718,13 +724,6 @@ */ create_pagetables: - - testl $CPUID_PGE, R(cpu_feature) - jz 1f - movl %cr4, %eax - orl $CR4_PGE, %eax - movl %eax, %cr4 -1: /* Find end of kernel image (rounded up to a page boundary). */ movl $R(_end),%esi Also I have another thing to be confirmed. Should we utilize TLB by enabling PGE bit at very later stage? I think it would be more efficient to cache page entries with G flag in multi-user environment, not in kernel bootstrap. If we enable PGE bit in locore.s, TLB could be occupied by entries which is referenced by initialization code (yes, most of them are executed only once). # but I could be wrong... Anyway, patch for this is attached here. Thanks. Index: initcpu.c =================================================================== RCS file: /home/ncvs/src/sys/i386/i386/initcpu.c,v retrieving revision 1.29 diff -u -r1.29 initcpu.c --- initcpu.c 2001/07/13 11:23:06 1.29 +++ initcpu.c 2001/08/08 15:35:51 @@ -847,3 +847,23 @@ printf("CR0=%x\n", cr0); } #endif /* DDB */ + +/* + * Enable CR4.PGE after kernel bootstrap. + */ + +static void +enable_i686_pge(void *unused) +{ + + if ((cpu_feature & CPUID_PGE) && + (cpu_id & 0xf00) == 0x600) { + load_cr4(rcr4() | CR4_PGE); + if (bootverbose) { + printf("P6 family processor PGE on\n"); + } + } +} + +SYSINIT(initcpu, SI_SUB_RUN_SCHEDULER, SI_ORDER_FIRST, enable_i686_pge, NULL) + To Unsubscribe: send mail to majordomo@FreeBSD.org with "unsubscribe freebsd-audit" in the body of the message
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