From owner-freebsd-arch@FreeBSD.ORG Fri Mar 6 21:58:38 2015 Return-Path: Delivered-To: freebsd-arch@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [8.8.178.115]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTPS id A8771868; Fri, 6 Mar 2015 21:58:38 +0000 (UTC) Received: from zxy.spb.ru (zxy.spb.ru [195.70.199.98]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 628D4967; Fri, 6 Mar 2015 21:58:38 +0000 (UTC) Received: from slw by zxy.spb.ru with local (Exim 4.84 (FreeBSD)) (envelope-from ) id 1YU0GR-000A0J-Bz; Sat, 07 Mar 2015 00:58:35 +0300 Date: Sat, 7 Mar 2015 00:58:35 +0300 From: Slawa Olhovchenkov To: Adrian Chadd Subject: Re: RFC: Simplfying hyperthreading distinctions Message-ID: <20150306215835.GB95179@zxy.spb.ru> References: <1640664.8z9mx3EOQs@ralph.baldwin.cx> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.23 (2014-03-12) X-SA-Exim-Connect-IP: X-SA-Exim-Mail-From: slw@zxy.spb.ru X-SA-Exim-Scanned: No (on zxy.spb.ru); SAEximRunCond expanded to false Cc: Andriy Gapon , "freebsd-arch@freebsd.org" X-BeenThere: freebsd-arch@freebsd.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: Discussion related to FreeBSD architecture List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 06 Mar 2015 21:58:38 -0000 On Fri, Mar 06, 2015 at 01:37:04PM -0800, Adrian Chadd wrote: > Hi! > > 1) I'd rather we leave them as SMT/HTT as they're slightly different > things. Who knows if intel will re-introduce this stuff in their more > embedded CPU line at a future time, or add another threading type in > the future. Being told about the distinction is nice. May be diagnostic HTT[SMT] or HTT[HTT] is best chois? > 2) I'd rather we had it more clearly defind - machdep.htt_allowed / > machdep.smt_allowed . Again, I'd rather have the distinction in case > Intel decide again to make their embedded things use old-style > threading. (The intel edison/galilleo boards use P1 style cores that > are low power, I can imagine a world where they reuse HTT for that.) I think this distinction don't need -- any way this setup is per-box. If you need to disable HTT/SMT -- you don't need to choise between machdep.htt_allowed and machdep.smt_allowed -- only one exist.