From owner-svn-src-head@freebsd.org Mon Jul 3 00:16:16 2017 Return-Path: Delivered-To: svn-src-head@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id AF2269B2AA1; Mon, 3 Jul 2017 00:16:16 +0000 (UTC) (envelope-from freebsd@pdx.rh.CN85.dnsmgr.net) Received: from pdx.rh.CN85.dnsmgr.net (br1.CN84in.dnsmgr.net [69.59.192.140]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 7045C7B451; Mon, 3 Jul 2017 00:16:15 +0000 (UTC) (envelope-from freebsd@pdx.rh.CN85.dnsmgr.net) Received: from pdx.rh.CN85.dnsmgr.net (localhost [127.0.0.1]) by pdx.rh.CN85.dnsmgr.net (8.13.3/8.13.3) with ESMTP id v630GElH044007; Sun, 2 Jul 2017 17:16:14 -0700 (PDT) (envelope-from freebsd@pdx.rh.CN85.dnsmgr.net) Received: (from freebsd@localhost) by pdx.rh.CN85.dnsmgr.net (8.13.3/8.13.3/Submit) id v630GE3Z044006; Sun, 2 Jul 2017 17:16:14 -0700 (PDT) (envelope-from freebsd) From: "Rodney W. Grimes" Message-Id: <201707030016.v630GE3Z044006@pdx.rh.CN85.dnsmgr.net> Subject: Re: svn commit: r320577 - head/sys/dev/sdhci In-Reply-To: <201707021913.v62JD1fh060028@repo.freebsd.org> To: Marius Strobl Date: Sun, 2 Jul 2017 17:16:14 -0700 (PDT) CC: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Reply-To: rgrimes@freebsd.org X-Mailer: ELM [version 2.4ME+ PL121h (25)] MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset=US-ASCII X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 03 Jul 2017 00:16:16 -0000 > Author: marius > Date: Sun Jul 2 19:13:01 2017 > New Revision: 320577 > URL: https://svnweb.freebsd.org/changeset/base/320577 > > Log: > Retry up to 20 ms to enable bus power as at least with some Intel ^^^^^^^ > SDHCI/eMMC controllers the first attempt after a D3 to D0 transition, > i. e. when the firmware has put the devices into D3 state before, > can fail. > > Modified: > head/sys/dev/sdhci/sdhci.c > > Modified: head/sys/dev/sdhci/sdhci.c > ============================================================================== > --- head/sys/dev/sdhci/sdhci.c Sun Jul 2 16:20:49 2017 (r320576) > +++ head/sys/dev/sdhci/sdhci.c Sun Jul 2 19:13:01 2017 (r320577) > @@ -366,6 +366,7 @@ sdhci_set_clock(struct sdhci_slot *slot, uint32_t cloc > static void > sdhci_set_power(struct sdhci_slot *slot, u_char power) > { > + int i; > uint8_t pwr; > > if (slot->power == power) > @@ -394,9 +395,20 @@ sdhci_set_power(struct sdhci_slot *slot, u_char power) > break; > } > WR1(slot, SDHCI_POWER_CONTROL, pwr); > - /* Turn on the power. */ > + /* > + * Turn on VDD1 power. Note that at least some Intel controllers can > + * fail to enable bus power on the first try after transiting from D3 > + * to D0, so we give them up to 20 ms. ^^^^^^^ > + */ > pwr |= SDHCI_POWER_ON; > - WR1(slot, SDHCI_POWER_CONTROL, pwr); > + for (i = 0; i < 20; i++) { ^^^ > + WR1(slot, SDHCI_POWER_CONTROL, pwr); > + if (RD1(slot, SDHCI_POWER_CONTROL) & SDHCI_POWER_ON) > + break; > + DELAY(100); ^^^^^ 20 x 100uS == 2mS, not 20ms. Please correct the loop, DELAY or the comments. > + } > + if (!(RD1(slot, SDHCI_POWER_CONTROL) & SDHCI_POWER_ON)) > + slot_printf(slot, "Bus power failed to enable"); > > if (slot->quirks & SDHCI_QUIRK_INTEL_POWER_UP_RESET) { > WR1(slot, SDHCI_POWER_CONTROL, pwr | 0x10); > > -- Rod Grimes rgrimes@freebsd.org