From owner-svn-src-head@FreeBSD.ORG Mon Sep 6 06:18:49 2010 Return-Path: Delivered-To: svn-src-head@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id CD0C6106566C; Mon, 6 Sep 2010 06:18:49 +0000 (UTC) (envelope-from jchandra@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:4f8:fff6::2c]) by mx1.freebsd.org (Postfix) with ESMTP id BB2858FC0C; Mon, 6 Sep 2010 06:18:49 +0000 (UTC) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.3/8.14.3) with ESMTP id o866InHA015913; Mon, 6 Sep 2010 06:18:49 GMT (envelope-from jchandra@svn.freebsd.org) Received: (from jchandra@localhost) by svn.freebsd.org (8.14.3/8.14.3/Submit) id o866InMf015909; Mon, 6 Sep 2010 06:18:49 GMT (envelope-from jchandra@svn.freebsd.org) Message-Id: <201009060618.o866InMf015909@svn.freebsd.org> From: "Jayachandran C." Date: Mon, 6 Sep 2010 06:18:49 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Subject: svn commit: r212248 - head/sys/mips/rmi X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 06 Sep 2010 06:18:50 -0000 Author: jchandra Date: Mon Sep 6 06:18:49 2010 New Revision: 212248 URL: http://svn.freebsd.org/changeset/base/212248 Log: XLR/XLS hardware interrupts should be programmed level triggered at the PIC. This should fix the interrupt releated issues seen after the interrupt handling re-write for SMP. Modified: head/sys/mips/rmi/iodi.c head/sys/mips/rmi/xlr_machdep.c head/sys/mips/rmi/xlr_pci.c Modified: head/sys/mips/rmi/iodi.c ============================================================================== --- head/sys/mips/rmi/iodi.c Mon Sep 6 04:15:49 2010 (r212247) +++ head/sys/mips/rmi/iodi.c Mon Sep 6 06:18:49 2010 (r212248) @@ -104,7 +104,7 @@ iodi_setup_intr(device_t dev, device_t c /* FIXME uart 1? */ cpu_establish_hardintr("uart", filt, intr, arg, PIC_UART_0_IRQ, flags, cookiep); - pic_setup_intr(PIC_IRT_UART_0_INDEX, PIC_UART_0_IRQ, 0x1, 0); + pic_setup_intr(PIC_IRT_UART_0_INDEX, PIC_UART_0_IRQ, 0x1, 1); } else if (strcmp(name, "rge") == 0 || strcmp(name, "nlge") == 0) { int irq; @@ -112,15 +112,15 @@ iodi_setup_intr(device_t dev, device_t c irq = (intptr_t)ires->__r_i; cpu_establish_hardintr("rge", filt, intr, arg, irq, flags, cookiep); - pic_setup_intr(irq - PIC_IRQ_BASE, irq, 0x1, 0); + pic_setup_intr(irq - PIC_IRQ_BASE, irq, 0x1, 1); } else if (strcmp(name, "ehci") == 0) { cpu_establish_hardintr("ehci", filt, intr, arg, PIC_USB_IRQ, flags, cookiep); - pic_setup_intr(PIC_USB_IRQ - PIC_IRQ_BASE, PIC_USB_IRQ, 0x1, 0); + pic_setup_intr(PIC_USB_IRQ - PIC_IRQ_BASE, PIC_USB_IRQ, 0x1, 1); } else if (strcmp(name, "ata") == 0) { xlr_establish_intr("ata", filt, intr, arg, PIC_PCMCIA_IRQ, flags, cookiep, bridge_pcmcia_ack); - pic_setup_intr(PIC_PCMCIA_IRQ - PIC_IRQ_BASE, PIC_PCMCIA_IRQ, 0x1, 0); + pic_setup_intr(PIC_PCMCIA_IRQ - PIC_IRQ_BASE, PIC_PCMCIA_IRQ, 0x1, 1); } return (0); } Modified: head/sys/mips/rmi/xlr_machdep.c ============================================================================== --- head/sys/mips/rmi/xlr_machdep.c Mon Sep 6 04:15:49 2010 (r212247) +++ head/sys/mips/rmi/xlr_machdep.c Mon Sep 6 06:18:49 2010 (r212248) @@ -297,7 +297,7 @@ xlr_pic_init(void) 2000, /* quality (adjusted in code) */ }; xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET); - int i, level, irq; + int i, irq; write_c0_eimr64(0ULL); mtx_init(&xlr_pic_lock, "pic", NULL, MTX_SPIN); @@ -306,17 +306,14 @@ xlr_pic_init(void) /* Initialize all IRT entries */ for (i = 0; i < PIC_NUM_IRTS; i++) { irq = PIC_INTR_TO_IRQ(i); - level = PIC_IS_EDGE_TRIGGERED(i); - - /* Bind all PIC irqs to cpu 0 */ - xlr_write_reg(mmio, PIC_IRT_0(i), 0x01); /* - * Use local scheduling and high polarity for all IRTs - * Invalidate all IRTs, by default + * Disable all IRTs. Set defaults (local scheduling, high + * polarity, level * triggered, and CPU irq) */ - xlr_write_reg(mmio, PIC_IRT_1(i), (level << 30) | (1 << 6) | - irq); + xlr_write_reg(mmio, PIC_IRT_1(i), (1 << 30) | (1 << 6) | irq); + /* Bind all PIC irqs to cpu 0 */ + xlr_write_reg(mmio, PIC_IRT_0(i), 0x01); } /* Setup timer 7 of PIC as a timestamp, no interrupts */ Modified: head/sys/mips/rmi/xlr_pci.c ============================================================================== --- head/sys/mips/rmi/xlr_pci.c Mon Sep 6 04:15:49 2010 (r212247) +++ head/sys/mips/rmi/xlr_pci.c Mon Sep 6 06:18:49 2010 (r212248) @@ -461,11 +461,11 @@ mips_platform_pci_setup_intr(device_t de if (xlr_board_info.is_xls == 0) { xlr_establish_intr(device_get_name(child), filt, intr, arg, PIC_PCIX_IRQ, flags, cookiep, bridge_pcix_ack); - pic_setup_intr(PIC_IRT_PCIX_INDEX, PIC_PCIX_IRQ, 0x1, 0); + pic_setup_intr(PIC_IRT_PCIX_INDEX, PIC_PCIX_IRQ, 0x1, 1); } else { xlr_establish_intr(device_get_name(child), filt, intr, arg, xlrirq, flags, cookiep, bridge_pcie_ack); - pic_setup_intr(xlrirq - PIC_IRQ_BASE, xlrirq, 0x1, 0); + pic_setup_intr(xlrirq - PIC_IRQ_BASE, xlrirq, 0x1, 1); } return (bus_generic_setup_intr(dev, child, irq, flags, filt, intr,