From owner-freebsd-mips@FreeBSD.ORG Tue Jun 4 16:03:59 2013 Return-Path: Delivered-To: freebsd-mips@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by hub.freebsd.org (Postfix) with ESMTP id A5D776C5; Tue, 4 Jun 2013 16:03:59 +0000 (UTC) (envelope-from jhb@freebsd.org) Received: from bigwig.baldwin.cx (bigwig.baldwin.cx [IPv6:2001:470:1f11:75::1]) by mx1.freebsd.org (Postfix) with ESMTP id 818CC1B18; Tue, 4 Jun 2013 16:03:59 +0000 (UTC) Received: from jhbbsd.localnet (unknown [209.249.190.124]) by bigwig.baldwin.cx (Postfix) with ESMTPSA id C88B1B953; Tue, 4 Jun 2013 12:03:58 -0400 (EDT) From: John Baldwin To: freebsd-arch@freebsd.org Subject: Re: Kernelspace C11 atomics for MIPS Date: Tue, 4 Jun 2013 09:56:00 -0400 User-Agent: KMail/1.13.5 (FreeBSD/8.2-CBSD-20110714-p25; KDE/4.5.5; amd64; ; ) References: <51ADA308.6040904@freebsd.org> In-Reply-To: MIME-Version: 1.0 Content-Type: Text/Plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Message-Id: <201306040956.01065.jhb@freebsd.org> X-Greylist: Sender succeeded SMTP AUTH, not delayed by milter-greylist-4.2.7 (bigwig.baldwin.cx); Tue, 04 Jun 2013 12:03:58 -0400 (EDT) Cc: mdf@freebsd.org, Andre Oppermann , freebsd-mips@freebsd.org, Ed Schouten X-BeenThere: freebsd-mips@freebsd.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: Porting FreeBSD to MIPS List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 04 Jun 2013 16:03:59 -0000 On Tuesday, June 04, 2013 9:12:36 am mdf@freebsd.org wrote: > Personally, I find both the C11 atomics and FreeBSD's annoying, > since "acquire" and "release" semantics are basically an x86 ism. PPC has > no notion of this; it has sync and isync and lwsync instructions which are > separate from the atomic set, but can be combined to create the same > effect. Except the PPC manual is exceptionally explicit about what > guarantees sync provides; it gives a mathematical ordering on loads/stores > i, j and which effects can be seen when. "Acquire" and "Release" seem to > be named because you kinda need one to acquire a lock and kinda need one to > release it. But the effect of ordering loads or stores or both doesn't > need to be dependent on the store/load, so putting the two together is just > an x86 convenience (and an annoyance on at least PPC). Actually, it came from ia64 (at least for FreeBSD's), not x86. :) However, it is still useful to think about, and they are barriers with respect to the load/store of the lock cookie. The requirement that the "acquire" blocks any subsequent loads/stores in program order from occurring until after the operation on the lock cookie succeeds and that "release" prevents any loads/stores frmo moving past the operation on the lock cookie is not quite the same as a traditional read or write barrier. acquire and release only require a barrier in one direction and enforce ordering on both reads and writes. -- John Baldwin