Date: Thu, 14 Feb 2008 22:13:55 +0200 From: Andriy Gapon <avg@icyb.net.ua> To: Bengt Ahlgren <bengta@sics.se> Cc: freebsd-acpi@freebsd.org Subject: Re: cx_lowest and CPU usage Message-ID: <47B4A103.7040801@icyb.net.ua> In-Reply-To: <uh7bq6jcveu.fsf@P142.sics.se> References: <479F0ED4.9030709@icyb.net.ua> <479F62D9.6080703@root.org> <47A33CCB.3090902@icyb.net.ua> <47B0C10F.6000109@icyb.net.ua> <47B4103A.6090902@icyb.net.ua> <uh7bq6jcveu.fsf@P142.sics.se>
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on 14/02/2008 19:14 Bengt Ahlgren said the following: > Andriy Gapon <avg@icyb.net.ua> writes: > >> on 11/02/2008 23:41 Andriy Gapon said the following: >>> on 01/02/2008 17:37 Andriy Gapon said the following: >>>>> Andriy Gapon wrote: >>>>>> Report for 7.0-RC1 on quite old hardware: 440BX-based motherboard, >>>>>> 450Mhz Pentium III (Katmai). >> [snip] >>>>>> There is a weird thing: if I change cx_lowest to C2 when the machine is >>>>>> completely idle, top shows that CPU usage for interrupts immediately >>>>>> jumps to almost 20%. Change cx_lowest to C1, CPU usage drops back to >>>>>> almost 0%. >>>>>> Is this normal ? >> [snip] >> >> I mis-reported the issue. Actually the above behavior occurs if I >> throttle CPU 50% (via acpi throttling) and I am not concerned about this >> at all. >> >> C2 has even stranger effects. >> On almost idle system, with cx_lowest=C1, top reports about 0-2% user, >> 0% nice, 0-2% system, 1-2% interrupt, 94-98% idle. >> After changing cx_lowest to C2, I see the following: 0-2% user, 0% nice, >> 0-2% system, 94-98% interrupt, 1-2% idle. > > I see a similar effect on my TP with Pentium-M when it is in C3 or C4, > but it's more in the order of 4% when in C3 and some 10-15% in C4. I > think that the additional time accounted to interrupts is due to the > time it takes to wake the CPU up from the particular Cx-state. My C3 > takes 85 (us?? or cycles???): I think that should be microseconds. But I think that the time spent while going to and from C2, along with time spent in C2, along with any other time spent by the "idle" thread should be accounted to idle time. I can not see a way how it could be accounted to interrupt time - CPU is not running any interrupt handlers at that time. > [root@P142 ~]# sysctl dev.cpu.0.cx_supported > dev.cpu.0.cx_supported: C1/1 C2/1 C3/85 > > [...] > >> Just in case, here's a little bit of sysctl output: >> dev.cpu.0.freq: 448 >> dev.cpu.0.freq_levels: 448/-1 224/-1 >> dev.cpu.0.cx_supported: C1/0 C2/90 >> dev.cpu.0.cx_lowest: C2 >> dev.cpu.0.cx_usage: 1.71% 98.28% > > With this slow CPU, a wakeup time of 90 from C2 could very well result > in this much interupt time. It just barely manages to wake up, > execute the clock interrupt and go to sleep again before the next > clock interrupt. What if you reduce HZ? Well, 90 microseconds is a reasonable time compared to 1 millisecond. That's why the standard permits up to 100 value (and up to 1000 for C3). I'll try smaller HZ for the sake of experiment, I think it might make a difference, but for a different reason. My suspicion is that relative long time of restoring from C2 might cause some sort of "auto synchronization" between hardclock and statclock (rtc in my case), so that (during mostly idle state) statclock is called at some particular moments. But this is a very far fetched hypothesis at this moment. -- Andriy Gapon
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