From owner-freebsd-questions@FreeBSD.ORG Tue Jun 13 16:06:06 2006 Return-Path: X-Original-To: freebsd-questions@freebsd.org Delivered-To: freebsd-questions@freebsd.org Received: from mx1.FreeBSD.org (mx1.freebsd.org [216.136.204.125]) by hub.freebsd.org (Postfix) with ESMTP id 2726816A477 for ; Tue, 13 Jun 2006 16:06:06 +0000 (UTC) (envelope-from pefo@opsycon.se) Received: from orion.opsycon.se (orion.opsycon.se [212.181.93.74]) by mx1.FreeBSD.org (Postfix) with ESMTP id 447FD43D53 for ; Tue, 13 Jun 2006 16:06:04 +0000 (GMT) (envelope-from pefo@opsycon.se) Received: from pundit.opsycon.se (pefo@pundit.opsycon.se [192.168.16.126]) by orion.opsycon.se (8.13.4/8.13.4) with ESMTP id k5DG5kJP012987; Tue, 13 Jun 2006 18:05:46 +0200 (CEST) From: Per =?iso-8859-1?q?Fogelstr=F6m?= Organization: Opsycon AB, Sweden To: rmk@rmkhome.com Date: Tue, 13 Jun 2006 18:05:17 +0200 User-Agent: KMail/1.9.1 References: <200606131223.k5DCNkcB021980@toad.rmkhome.com> In-Reply-To: <200606131223.k5DCNkcB021980@toad.rmkhome.com> MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200606131805.18778.pefo@opsycon.se> X-Mailman-Approved-At: Tue, 13 Jun 2006 16:20:12 +0000 Cc: John Nemeth , misc@openbsd.org, Otto Moerbeek , Ted Unangst , Ted Mittelstaedt , Marcus Watts , freebsd-questions@freebsd.org, =?iso-8859-1?q?H=E1morszky?= =?iso-8859-1?q?_Bal=E1zs?= , Johnny Billquist , netbsd-users@netbsd.org, Nikolas Britton Subject: Re: wikipedia article X-BeenThere: freebsd-questions@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: User questions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 13 Jun 2006 16:06:06 -0000 On Tuesday 13 June 2006 14:23, Rick Kelly wrote: > Johnny Billquist said: > >> There's actually a cheesy way to do demand paging with microprocessors > >> that don't support demand paging (such as the original 68000--another > >> "16 bit" machine). The way to do this is to run two processors in > >> parallel but skewed by one instruction. If the first one does a bad > >> memory fetch, then the second one will not have fetched the instruction > >> causing the fault so contains restartable machine state. Masscomp sold > >> a machine like this once. > > > >Didn't the first Apollos do this? > > And also the Sun 1. IIRC it was simpler than that. When the first cpu caused a 'miss' it was put in wait and cpu 2 handled the pagein and then released cpu 1. Keeping the two cpus synched, one instruction apart would have been too complicated if not impossible...