Date: Wed, 8 Nov 2006 19:08:57 GMT From: Sam Leffler <sam@FreeBSD.org> To: Perforce Change Reviews <perforce@freebsd.org> Subject: PERFORCE change 109541 for review Message-ID: <200611081908.kA8J8vfE047204@repoman.freebsd.org>
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http://perforce.freebsd.org/chv.cgi?CH=109541 Change 109541 by sam@sam_ebb on 2006/11/08 19:08:34 whitespace changes; also nuke defines brought over from intel code that we'll never use Affected files ... .. //depot/projects/arm/src/sys/arm/xscale/ixp425/if_npe.c#18 edit .. //depot/projects/arm/src/sys/arm/xscale/ixp425/if_npereg.h#5 edit Differences ... ==== //depot/projects/arm/src/sys/arm/xscale/ixp425/if_npe.c#18 (text+ko) ==== @@ -939,6 +939,7 @@ */ WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_RESET); DELAY(NPE_MAC_RESET_DELAY); + /* configure MAC to generate MDC clock */ WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_MDC_EN); /* disable transmitter and reciver in the MAC */ ==== //depot/projects/arm/src/sys/arm/xscale/ixp425/if_npereg.h#5 (text+ko) ==== @@ -62,10 +62,14 @@ /* * NPE/NPE tx/rx descriptor format. This data structure has an - * area used by the Intel NPE s/w support followed by an area - * shared with ucode running in the NPE. Since we don't use any - * of the Intel code all the s/w area is free for us to use as we - * choose--only the npe area layout and alignment must be honored. + * area used by the driver followed by an area shared with ucode + * running in the NPE. The latter must be cacheline-aligned; + * hence the unused space in the s/w area. We allocate NPE_MAXSEG + * "descriptors" per buffer; this allows us to do minimal s/g. + * The number of descriptors can be expanded but doing so uses + * memory so should be done with care. + * + * These buffers are setup in uncached memory. */ #define NPE_MAXSEG 3 /* empirically selected */ @@ -116,93 +120,94 @@ #define NPE_SETLOOPBACK 0x12 /* enable/disable loopback */ /* ... XXX more */ +#define NPE_MAC_MSGID_SHL 24 +#define NPE_MAC_PORTID_SHL 16 + /* - * MAC register definitions + * MAC register definitions; see section + * 15.2 of the Intel Developers Manual. */ -#define NPE_MAC_TX_CNTRL1 0x000 -#define NPE_MAC_TX_CNTRL2 0x004 -#define NPE_MAC_RX_CNTRL1 0x010 -#define NPE_MAC_RX_CNTRL2 0x014 -#define NPE_MAC_RANDOM_SEED 0x020 -#define NPE_MAC_THRESH_P_EMPTY 0x030 -#define NPE_MAC_THRESH_P_FULL 0x038 -#define NPE_MAC_BUF_SIZE_TX 0x040 -#define NPE_MAC_TX_DEFER 0x050 -#define NPE_MAC_RX_DEFER 0x054 -#define NPE_MAC_TX_TWO_DEFER_1 0x060 -#define NPE_MAC_TX_TWO_DEFER_2 0x064 -#define NPE_MAC_SLOT_TIME 0x070 -#define NPE_MAC_MDIO_CMD_1 0x080 -#define NPE_MAC_MDIO_CMD_2 0x084 -#define NPE_MAC_MDIO_CMD_3 0x088 -#define NPE_MAC_MDIO_CMD_4 0x08c -#define NPE_MAC_MDIO_STS_1 0x090 -#define NPE_MAC_MDIO_STS_2 0x094 -#define NPE_MAC_MDIO_STS_3 0x098 -#define NPE_MAC_MDIO_STS_4 0x09c -#define NPE_MAC_ADDR_MASK_1 0x0A0 -#define NPE_MAC_ADDR_MASK_2 0x0A4 -#define NPE_MAC_ADDR_MASK_3 0x0A8 -#define NPE_MAC_ADDR_MASK_4 0x0AC -#define NPE_MAC_ADDR_MASK_5 0x0B0 -#define NPE_MAC_ADDR_MASK_6 0x0B4 -#define NPE_MAC_ADDR_1 0x0C0 -#define NPE_MAC_ADDR_2 0x0C4 -#define NPE_MAC_ADDR_3 0x0C8 -#define NPE_MAC_ADDR_4 0x0CC -#define NPE_MAC_ADDR_5 0x0D0 -#define NPE_MAC_ADDR_6 0x0D4 -#define NPE_MAC_INT_CLK_THRESH 0x0E0 -#define NPE_MAC_UNI_ADDR_1 0x0F0 -#define NPE_MAC_UNI_ADDR_2 0x0F4 -#define NPE_MAC_UNI_ADDR_3 0x0F8 -#define NPE_MAC_UNI_ADDR_4 0x0FC -#define NPE_MAC_UNI_ADDR_5 0x100 -#define NPE_MAC_UNI_ADDR_6 0x104 -#define NPE_MAC_CORE_CNTRL 0x1FC +#define NPE_MAC_TX_CNTRL1 0x000 +#define NPE_MAC_TX_CNTRL2 0x004 +#define NPE_MAC_RX_CNTRL1 0x010 +#define NPE_MAC_RX_CNTRL2 0x014 +#define NPE_MAC_RANDOM_SEED 0x020 +#define NPE_MAC_THRESH_P_EMPTY 0x030 +#define NPE_MAC_THRESH_P_FULL 0x038 +#define NPE_MAC_BUF_SIZE_TX 0x040 +#define NPE_MAC_TX_DEFER 0x050 +#define NPE_MAC_RX_DEFER 0x054 +#define NPE_MAC_TX_TWO_DEFER_1 0x060 +#define NPE_MAC_TX_TWO_DEFER_2 0x064 +#define NPE_MAC_SLOT_TIME 0x070 +#define NPE_MAC_MDIO_CMD_1 0x080 +#define NPE_MAC_MDIO_CMD_2 0x084 +#define NPE_MAC_MDIO_CMD_3 0x088 +#define NPE_MAC_MDIO_CMD_4 0x08c +#define NPE_MAC_MDIO_STS_1 0x090 +#define NPE_MAC_MDIO_STS_2 0x094 +#define NPE_MAC_MDIO_STS_3 0x098 +#define NPE_MAC_MDIO_STS_4 0x09c +#define NPE_MAC_ADDR_MASK_1 0x0A0 +#define NPE_MAC_ADDR_MASK_2 0x0A4 +#define NPE_MAC_ADDR_MASK_3 0x0A8 +#define NPE_MAC_ADDR_MASK_4 0x0AC +#define NPE_MAC_ADDR_MASK_5 0x0B0 +#define NPE_MAC_ADDR_MASK_6 0x0B4 +#define NPE_MAC_ADDR_1 0x0C0 +#define NPE_MAC_ADDR_2 0x0C4 +#define NPE_MAC_ADDR_3 0x0C8 +#define NPE_MAC_ADDR_4 0x0CC +#define NPE_MAC_ADDR_5 0x0D0 +#define NPE_MAC_ADDR_6 0x0D4 +#define NPE_MAC_INT_CLK_THRESH 0x0E0 +#define NPE_MAC_UNI_ADDR_1 0x0F0 +#define NPE_MAC_UNI_ADDR_2 0x0F4 +#define NPE_MAC_UNI_ADDR_3 0x0F8 +#define NPE_MAC_UNI_ADDR_4 0x0FC +#define NPE_MAC_UNI_ADDR_5 0x100 +#define NPE_MAC_UNI_ADDR_6 0x104 +#define NPE_MAC_CORE_CNTRL 0x1FC -#define NPE_MAC_ADDR_MASK(i) (NPE_MAC_ADDR_MASK_1 + ((i)<<2)) -#define NPE_MAC_ADDR(i) (NPE_MAC_ADDR_1 + ((i)<<2)) -#define NPE_MAC_UNI_ADDR(i) (NPE_MAC_UNI_ADDR_1 + ((i)<<2)) +#define NPE_MAC_ADDR_MASK(i) (NPE_MAC_ADDR_MASK_1 + ((i)<<2)) +#define NPE_MAC_ADDR(i) (NPE_MAC_ADDR_1 + ((i)<<2)) +#define NPE_MAC_UNI_ADDR(i) (NPE_MAC_UNI_ADDR_1 + ((i)<<2)) /* * Bit definitions */ /* TX Control Register 1*/ -#define NPE_TX_CNTRL1_TX_EN (1<<0) /* enable TX engine */ -#define NPE_TX_CNTRL1_DUPLEX (1<<1) /* select half duplex */ -#define NPE_TX_CNTRL1_RETRY (1<<2) /* auto-retry on collision */ -#define NPE_TX_CNTRL1_PAD_EN (1<<3) /* pad frames <64 bytes */ -#define NPE_TX_CNTRL1_FCS_EN (1<<4) /* append FCS */ -#define NPE_TX_CNTRL1_2DEFER (1<<5) /* select 2-part deferral */ -#define NPE_TX_CNTRL1_RMII (1<<6) +#define NPE_TX_CNTRL1_TX_EN 0x01 /* enable TX engine */ +#define NPE_TX_CNTRL1_DUPLEX 0x02 /* select half duplex */ +#define NPE_TX_CNTRL1_RETRY 0x04 /* auto-retry on collision */ +#define NPE_TX_CNTRL1_PAD_EN 0x08 /* pad frames <64 bytes */ +#define NPE_TX_CNTRL1_FCS_EN 0x10 /* append FCS */ +#define NPE_TX_CNTRL1_2DEFER 0x20 /* select 2-part deferral */ +#define NPE_TX_CNTRL1_RMII 0x40 /* TX Control Register 2 */ -#define NPE_TX_CNTRL2_RETRIES_MASK 0xf /* max retry count */ +#define NPE_TX_CNTRL2_RETRIES_MASK 0xf /* max retry count */ /* RX Control Register 1 */ -#define NPE_RX_CNTRL1_RX_EN (1<<0) /* enable RX engine */ -#define NPE_RX_CNTRL1_PADSTRIP_EN (1<<1) /* strip frame padding */ -#define NPE_RX_CNTRL1_CRC_EN (1<<2) /* include CRC in RX frame */ -#define NPE_RX_CNTRL1_PAUSE_EN (1<<3) /* detect Pause frames */ -#define NPE_RX_CNTRL1_LOOP_EN (1<<4) /* loopback tx/rx */ -#define NPE_RX_CNTRL1_ADDR_FLTR_EN (1<<5) /* enable address filtering */ -#define NPE_RX_CNTRL1_RX_RUNT_EN (1<<6) /* enable RX of runt frames */ -#define NPE_RX_CNTRL1_BCAST_DIS (1<<7) /* discard broadcast frames */ +#define NPE_RX_CNTRL1_RX_EN 0x01 /* enable RX engine */ +#define NPE_RX_CNTRL1_PADSTRIP_EN 0x02 /* strip frame padding */ +#define NPE_RX_CNTRL1_CRC_EN 0x04 /* include CRC in RX frame */ +#define NPE_RX_CNTRL1_PAUSE_EN 0x08 /* detect Pause frames */ +#define NPE_RX_CNTRL1_LOOP_EN 0x10 /* loopback tx/rx */ +#define NPE_RX_CNTRL1_ADDR_FLTR_EN 0x20 /* enable address filtering */ +#define NPE_RX_CNTRL1_RX_RUNT_EN 0x40 /* enable RX of runt frames */ +#define NPE_RX_CNTRL1_BCAST_DIS 0x80 /* discard broadcast frames */ /* RX Control Register 2 */ -#define NPE_RX_CNTRL2_DEFER_EN (1<<0) +#define NPE_RX_CNTRL2_DEFER_EN 0x01 /* Core Control Register */ -#define NPE_CORE_RESET (1<<0) /* MAC reset state */ -#define NPE_CORE_RX_FIFO_FLUSH (1<<1) /* flush RX FIFO */ -#define NPE_CORE_TX_FIFO_FLUSH (1<<2) /* flush TX FIFO */ -#define NPE_CORE_SEND_JAM (1<<3) /* send JAM on packet RX */ -#define NPE_CORE_MDC_EN (1<<4) /* IXP42X drives MDC clock */ - -/* 1st bit of 1st MAC octet */ -#define NPE_ETH_MAC_BCAST_MCAST_BIT ( 1) +#define NPE_CORE_RESET 0x01 /* MAC reset state */ +#define NPE_CORE_RX_FIFO_FLUSH 0x02 /* flush RX FIFO */ +#define NPE_CORE_TX_FIFO_FLUSH 0x04 /* flush TX FIFO */ +#define NPE_CORE_SEND_JAM 0x08 /* send JAM on packet RX */ +#define NPE_CORE_MDC_EN 0x10 /* IXP42X drives MDC clock */ /* * Stat block returned by NPE with NPE_GETSTATS msg. @@ -235,74 +240,22 @@ /* * Default values */ -#define NPE_TX_CNTRL1_DEFAULT \ - (NPE_TX_CNTRL1_TX_EN | NPE_TX_CNTRL1_RETRY | NPE_TX_CNTRL1_FCS_EN | \ - NPE_TX_CNTRL1_2DEFER | NPE_TX_CNTRL1_PAD_EN) -#define NPE_TX_MAX_RETRIES_DEFAULT 0x0f -#define NPE_RX_CNTRL1_DEFAULT \ - (NPE_RX_CNTRL1_CRC_EN | NPE_RX_CNTRL1_RX_EN) -#define NPE_RX_CNTRL2_DEFAULT 0x0 +#define NPE_MAC_INT_CLK_THRESH_DEFAULT 0x1 -/* Thresholds determined by NPE firmware FS */ -#define NPE_MAC_THRESH_P_EMPTY_DEFAULT 0x12 -#define NPE_MAC_THRESH_P_FULL_DEFAULT 0x30 +#define NPE_MAC_RESET_DELAY 1 -/* Number of bytes that must be in the tx fifo before - transmission commences*/ -#define NPE_MAC_BUF_SIZE_TX_DEFAULT 0x8 - -/* One-part deferral values */ -#define NPE_MAC_TX_DEFER_DEFAULT 0x15 -#define NPE_MAC_RX_DEFER_DEFAULT 0x16 - -/* Two-part deferral values... */ -#define NPE_MAC_TX_TWO_DEFER_1_DEFAULT 0x08 -#define NPE_MAC_TX_TWO_DEFER_2_DEFAULT 0x07 - -/* This value applies to MII */ -#define NPE_MAC_SLOT_TIME_DEFAULT 0x80 - /* This value applies to RMII */ #define NPE_MAC_SLOT_TIME_RMII_DEFAULT 0xFF -#define NPE_MAC_ADDR_MASK_DEFAULT 0xFF - -#define NPE_MAC_INT_CLK_THRESH_DEFAULT 0x1 -/*The following is a value chosen at random*/ -#define NPE_RANDOM_SEED_DEFAULT 0x8 - -/*By default we must configure the MAC to generate the - MDC clock*/ -#define NPE_CORE_DEFAULT NPE_CORE_MDC_EN - -#define IXP400_ETH_ACC_MAX_PHY 2 -#define IXP400_ETH_ACC_MAX_AN_ENTRIES 20 -#define NPE_MAC_RESET_DELAY 1 - -#define NPE_MAC_ALL_BITS_SET 0xFF - -#define NPE_MAC_MSGID_SHL 24 -#define NPE_MAC_PORTID_SHL 16 - -#define NPE_PORT_DISABLE_DELAY_MSECS 20 -#define NPE_PORT_DISABLE_DELAY_COUNT 200 /* 4 seconds timeout */ -#define NPE_PORT_DISABLE_RETRY_COUNT 3 -#define NPE_MIB_STATS_DELAY_MSECS 2000 /* 2 seconds delay for ethernet stats */ - /* * MII definitions - these have been verified against the LXT971 and LXT972 PHYs */ +#define NPE_MII_REG_SHL 16 +#define NPE_MII_ADDR_SHL 21 -#define IXP400_ETH_ACC_MII_MAX_REG 32 /* max register per phy */ - -#define NPE_MII_REG_SHL 16 -#define NPE_MII_ADDR_SHL 21 - -/* Definitions for MII access routines*/ - /* NB: shorthands for mii bus mdio routines */ -#define NPE_MAC_MDIO_CMD NPE_MAC_MDIO_CMD_1 -#define NPE_MAC_MDIO_STS NPE_MAC_MDIO_STS_1 +#define NPE_MAC_MDIO_CMD NPE_MAC_MDIO_CMD_1 +#define NPE_MAC_MDIO_STS NPE_MAC_MDIO_STS_1 #define NPE_MII_GO (1<<31) #define NPE_MII_WRITE (1<<26) @@ -315,12 +268,7 @@ #define NPE_MII_PHY_NULL 0xff /* PHY is not present */ #define NPE_MII_PHY_DEF_ADDR 0x0 /* default PHY's logical address */ -#ifndef NPE_MII_MONITOR_DELAY -# define NPE_MII_MONITOR_DELAY 0x5 /* in seconds */ -#endif - /* Register definition */ - #define NPE_MII_CTRL_REG 0x0 /* Control Register */ #define NPE_MII_STAT_REG 0x1 /* Status Register */ #define NPE_MII_PHY_ID1_REG 0x2 /* PHY identifier 1 Register */
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