From owner-p4-projects@FreeBSD.ORG Sun Jun 13 13:27:25 2004 Return-Path: Delivered-To: p4-projects@freebsd.org Received: by hub.freebsd.org (Postfix, from userid 32767) id E74EE16A4D1; Sun, 13 Jun 2004 13:27:24 +0000 (GMT) Delivered-To: perforce@freebsd.org Received: from mx1.FreeBSD.org (mx1.freebsd.org [216.136.204.125]) by hub.freebsd.org (Postfix) with ESMTP id 9B50716A4CE for ; Sun, 13 Jun 2004 13:27:24 +0000 (GMT) Received: from repoman.freebsd.org (repoman.freebsd.org [216.136.204.115]) by mx1.FreeBSD.org (Postfix) with ESMTP id 811F143D31 for ; Sun, 13 Jun 2004 13:27:24 +0000 (GMT) (envelope-from jmallett@freebsd.org) Received: from repoman.freebsd.org (localhost [127.0.0.1]) by repoman.freebsd.org (8.12.11/8.12.11) with ESMTP id i5DD5cZP041330 for ; Sun, 13 Jun 2004 13:05:38 GMT (envelope-from jmallett@freebsd.org) Received: (from perforce@localhost) by repoman.freebsd.org (8.12.11/8.12.11/Submit) id i5DD5bqV041327 for perforce@freebsd.org; Sun, 13 Jun 2004 13:05:37 GMT (envelope-from jmallett@freebsd.org) Date: Sun, 13 Jun 2004 13:05:37 GMT Message-Id: <200406131305.i5DD5bqV041327@repoman.freebsd.org> X-Authentication-Warning: repoman.freebsd.org: perforce set sender to jmallett@freebsd.org using -f From: Juli Mallett To: Perforce Change Reviews Subject: PERFORCE change 54816 for review X-BeenThere: p4-projects@freebsd.org X-Mailman-Version: 2.1.1 Precedence: list List-Id: p4 projects tree changes List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 13 Jun 2004 13:27:25 -0000 http://perforce.freebsd.org/chv.cgi?CH=54816 Change 54816 by jmallett@jmallett_oingo on 2004/06/13 13:05:08 Push IMC address over to hints. Affected files ... .. //depot/projects/mips/sys/mips/conf/INDY.hints#2 edit .. //depot/projects/mips/sys/mips/sgimips/imc/imc.c#7 edit Differences ... ==== //depot/projects/mips/sys/mips/conf/INDY.hints#2 (text+ko) ==== @@ -1,4 +1,5 @@ -# $P4: //depot/projects/mips/sys/mips/conf/INDY.hints#1 $ +# $P4: //depot/projects/mips/sys/mips/conf/INDY.hints#2 $ hint.hpc.0.port="0x1fb80000" hint.hpc.1.port="0x1fb00000" hint.hpc.2.port="0x1f980000" +hint.imc.0.port="0x1fa00000" ==== //depot/projects/mips/sys/mips/sgimips/imc/imc.c#7 (text+ko) ==== @@ -23,7 +23,7 @@ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * - * $P4: //depot/projects/mips/sys/mips/sgimips/imc/imc.c#6 $ + * $P4: //depot/projects/mips/sys/mips/sgimips/imc/imc.c#7 $ */ #include @@ -62,7 +62,7 @@ }; static driver_t imc_driver = { - "imc", imc_methods, 1 + "imc", imc_methods, sizeof (long) }; static const char *imc_devices[] = { @@ -70,8 +70,6 @@ NULL }; -static const u_long imc_port = 0x1fa00000; /* XXX hints */ - #define IMC_READ_4(port, r) \ bus_space_read_4(device_space_tag, (port), (r)) @@ -82,6 +80,9 @@ imc_probe(device_t dev) { const char **namep; + int error; + long *scp; + long port; if (device_get_unit(dev) != 0) return (ENXIO); @@ -89,6 +90,13 @@ switch (mach_type) { case MACH_SGI_IP22: device_set_desc(dev, "IMC Bus"); + error = resource_long_value(device_get_name(dev), + device_get_unit(dev), + "port", &port); + if (error != 0) + return (ENODEV); + scp = device_get_softc(dev); + *scp = port; for (namep = imc_devices; *namep != NULL; namep++) device_add_child(dev, *namep, -1); return (0); @@ -100,10 +108,15 @@ static int imc_attach(device_t dev) { + long port; + long *scp; uint32_t reg; uint32_t sysid; - sysid = IMC_READ_4(imc_port, IMC_SYSID); + scp = device_get_softc(dev); + port = *scp; + + sysid = IMC_READ_4(port, IMC_SYSID); /* IP24 lies about having EISA. Don't believe its sugary-sweet lies! */ if (mach_subtype == MACH_SGI_IP22_GUINESS) sysid &= ~IMC_SYSID_HAVEISA; @@ -111,8 +124,8 @@ sysid & IMC_SYSID_HAVEISA ? "present" : "not present"); /* Clear error status. */ - IMC_WRITE_4(imc_port, IMC_CPU_ERRSTAT, 0); - IMC_WRITE_4(imc_port, IMC_GIO_ERRSTAT, 0); + IMC_WRITE_4(port, IMC_CPU_ERRSTAT, 0); + IMC_WRITE_4(port, IMC_GIO_ERRSTAT, 0); /* * Enable parity reporting on GIO/main memory transactions. @@ -122,15 +135,15 @@ * has the opposite sense... Turning it on turns the checks off!). * Finally, turn on interrupt writes to the CPU from the MC. */ - reg = IMC_READ_4(imc_port, IMC_CPUCTRL0); + reg = IMC_READ_4(port, IMC_CPUCTRL0); reg &= ~IMC_CPUCTRL0_NCHKMEMPAR; reg |= (IMC_CPUCTRL0_GPR | IMC_CPUCTRL0_MPR | IMC_CPUCTRL0_INTENA); - IMC_WRITE_4(imc_port, IMC_CPUCTRL0, reg); + IMC_WRITE_4(port, IMC_CPUCTRL0, reg); /* Setup the MC write buffer depth */ - reg = IMC_READ_4(imc_port, IMC_CPUCTRL1); + reg = IMC_READ_4(port, IMC_CPUCTRL1); reg = (reg & ~IMC_CPUCTRL1_MCHWMSK) | 13; - IMC_WRITE_4(imc_port, IMC_CPUCTRL1, reg); + IMC_WRITE_4(port, IMC_CPUCTRL1, reg); /* * Set GIO64 arbitrator configuration register: @@ -139,7 +152,7 @@ * on the graphics variant present and I'm not sure how to figure * that out or 100% sure what the correct settings are for each. */ - reg = IMC_READ_4(imc_port, IMC_GIO64ARB); + reg = IMC_READ_4(port, IMC_GIO64ARB); reg &= (IMC_GIO64ARB_GRX64 | IMC_GIO64ARB_GRXRT | IMC_GIO64ARB_GRXMST); /* GIO64 invariant for all IP22 platforms: one GIO bus, HPC1 @ 64 */ @@ -168,7 +181,7 @@ } break; } - IMC_WRITE_4(imc_port, IMC_GIO64ARB, reg); + IMC_WRITE_4(port, IMC_GIO64ARB, reg); bus_generic_attach(dev);