From owner-cvs-src-old@FreeBSD.ORG Mon Dec 21 18:34:39 2009 Return-Path: Delivered-To: cvs-src-old@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 8BD4D1065694 for ; Mon, 21 Dec 2009 18:34:39 +0000 (UTC) (envelope-from yongari@FreeBSD.org) Received: from repoman.freebsd.org (repoman.freebsd.org [IPv6:2001:4f8:fff6::29]) by mx1.freebsd.org (Postfix) with ESMTP id 79D918FC1B for ; Mon, 21 Dec 2009 18:34:39 +0000 (UTC) Received: from repoman.freebsd.org (localhost [127.0.0.1]) by repoman.freebsd.org (8.14.3/8.14.3) with ESMTP id nBLIYdo7058514 for ; Mon, 21 Dec 2009 18:34:39 GMT (envelope-from yongari@repoman.freebsd.org) Received: (from svn2cvs@localhost) by repoman.freebsd.org (8.14.3/8.14.3/Submit) id nBLIYdTw058513 for cvs-src-old@freebsd.org; Mon, 21 Dec 2009 18:34:39 GMT (envelope-from yongari@repoman.freebsd.org) Message-Id: <200912211834.nBLIYdTw058513@repoman.freebsd.org> X-Authentication-Warning: repoman.freebsd.org: svn2cvs set sender to yongari@repoman.freebsd.org using -f From: Pyun YongHyeon Date: Mon, 21 Dec 2009 18:34:18 +0000 (UTC) To: cvs-src-old@freebsd.org X-FreeBSD-CVS-Branch: RELENG_8 Subject: cvs commit: src/sys/dev/et if_et.c if_etvar.h X-BeenThere: cvs-src-old@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: **OBSOLETE** CVS commit messages for the src tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 21 Dec 2009 18:34:39 -0000 yongari 2009-12-21 18:34:18 UTC FreeBSD src repository Modified files: (Branch: RELENG_8) sys/dev/et if_et.c if_etvar.h Log: SVN rev 200789 on 2009-12-21 18:34:18Z by yongari MFC r199558,199561 r199558: Use bus_{read,write}_4 rather than bus_space_{read,write}_4. r199561: Use capability pointer to access PCIe registers rather than directly access them at fixed address. Frequently the register offset could be changed if additional PCI capabilities are added to controller. One odd thing is ET_PCIR_L0S_L1_LATENCY register. I think it's PCIe link capabilities register but the location of the register does not match with PCIe capability pointer + offset. I'm not sure it's shadow register of PCIe link capabilities register. Revision Changes Path 1.3.2.5 +26 -20 src/sys/dev/et/if_et.c 1.1.4.5 +2 -4 src/sys/dev/et/if_etvar.h