From owner-freebsd-hackers@freebsd.org Tue Aug 21 05:14:29 2018 Return-Path: Delivered-To: freebsd-hackers@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 63FE51089305; Tue, 21 Aug 2018 05:14:29 +0000 (UTC) (envelope-from danny@cs.huji.ac.il) Received: from kabab.cs.huji.ac.il (kabab.cs.huji.ac.il [132.65.116.210]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id C57B873104; Tue, 21 Aug 2018 05:14:28 +0000 (UTC) (envelope-from danny@cs.huji.ac.il) Received: from bach.cs.huji.ac.il ([132.65.80.20]) by kabab.cs.huji.ac.il with esmtp id 1fryzc-000NY9-Sb; Tue, 21 Aug 2018 08:14:12 +0300 From: Daniel Braniss Message-Id: <9F8E2C3D-61D6-487E-A19D-6B91FBAD930B@cs.huji.ac.il> Mime-Version: 1.0 (Mac OS X Mail 11.5 \(3445.9.1\)) Subject: Re: Need a clarification regarding I2C bus frequency in FreeBSD Date: Tue, 21 Aug 2018 08:14:11 +0300 In-Reply-To: <20180820181322.71607854@ernst.home> Cc: Mark Millard via freebsd-hackers , Mark Millard , Rajesh Kumar , freebsd-drivers@freebsd.org, Ian Lepore To: gljennjohn@gmail.com References: <1534523216.27158.17.camel@freebsd.org> <1534702861.27158.36.camel@freebsd.org> <1534771095.27158.46.camel@freebsd.org> <35F2C250-B4CB-4C53-BF8F-43C338022E34@yahoo.com> <20180820181322.71607854@ernst.home> X-Mailer: Apple Mail (2.3445.9.1) Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-Content-Filtered-By: Mailman/MimeDel 2.1.27 X-BeenThere: freebsd-hackers@freebsd.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: Technical Discussions relating to FreeBSD List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 21 Aug 2018 05:14:29 -0000 > On 20 Aug 2018, at 19:13, Gary Jennejohn wrote: >=20 > On Mon, 20 Aug 2018 07:16:15 -0700 > Mark Millard via freebsd-hackers > wrote: >=20 >> On 2018-Aug-20, at 6:18 AM, Ian Lepore wrote: >>=20 >>> On Mon, 2018-08-20 at 11:13 +0300, Daniel Braniss wrote: =20 >>>>=20 >>>>>=20 >>>>> On 20 Aug 2018, at 09:49, Daniel Braniss = wrote: >>>>>=20 >>>>>> . . . =20 >>>>>=20 >>>>> hi, >>>>> I have similar issues with the allwinner/twsi but I do have a = Saleae Logic and here is a nice picture: =20 >>>> ah, maybe this is better: >>>> = https://cs.huji.ac.il/~danny/Screen%20Shot%202018-08-20%20at%2011.06.43.pn= g =20 >>> . . . >>> This has nothing to do with the twsi driver, this is about the ig4 >>> driver (found in sys/dev/ichiic). >>>=20 >>> That screenshot seems to show a bus running at 100KHz like it should >>> (although the 62:38 duty cycle is a bit suspicious). =20 >>=20 >> Being a logic analyzer display, it my just be that the threshold >> was off from the optimal value. The waveform shape is not really >> visible. >>=20 >> The logic analyzer output also shows a thick "rising" edge without = the >> uparrow symbol. My guess would be that is a rising/falling/rising >> sequence that on the scale in use does not show space between edges. = In >> other words: a glitch on the leading edge side of the intended pulse. >> This too might be tied to the threshold used vs . the actual signal >> properties: no way to tell from what is shown. >>=20 >=20 > I have two of these logic analyzers and they definitely do a > major clean up of the signals displayed. >=20 > Things like overshoot and ringing, which can be seen on an > oscilloscope, do not appear on what the logic analyzer displays. >=20 > I suspect the purpose of the trace was simply to show the 100KHz > SCL. >=20 yup, I connected the logic analyzer to check the frequency, which was not changing, later I confirmed by looking at the source that it=E2=80= =99s set at a constant 100KHz. > --=20 > Gary Jennejohn