Date: Fri, 8 Nov 1996 10:43:12 -0600 (CST) From: Joe Greco <jgreco@brasil.moneng.mei.com> To: rv@groa.uct.ac.za (Russell Vincent) Cc: jgreco@brasil.moneng.mei.com, current@freebsd.org, hardware@freebsd.org Subject: Re: Large RAM on ASUS P/E-P55T2P4D Message-ID: <199611081643.KAA12381@brasil.moneng.mei.com> In-Reply-To: <m0vLr4n-0004vzC@groa.uct.ac.za> from "Russell Vincent" at Nov 8, 96 03:34:28 pm
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> Joe Greco wrote (about the ASUS P/E-P55T2P4D): > > I can't get anything more than 192MB to work reliably on this board > > (6 x 32MB SIMM modules) - unless we go with the mega mondo $$$$ 64MB > > SIMM's.. and even those I have doubts about. We put the 4 that we > > have on a P/I-P55T2P4 board and it refused to work until we relaxed > > the RAM timing to 70ns. Gives me a sick feeling. > > Seems I may be encountering this problem on some of my 5 machines > with 256MB, after all. Our supplier has just pointed me to pages 12-33 of: > > http://www.intel.com/design/pcisets/datashts/inte2.htm > > (which I am struggling to download on our poor international link). You are really looking for the data on MAD... 3.2.13. DRAMEC - DRAM EXTENDED CONTROL REGISTER Address Offset: 56h Default Value: 00h Access: Read/Write This 8-bit register contains additional controls for main memory DRAM operating modes and features. [...] Bit Descriptions 2:1 Memory Address Drive Strength (MAD): This field controls the strength of the output buffers driving the MA and MWE# pins. Bit 2 Bit 1 MAA[1:0]/MAB[1:0] MA[11:2]/MWE# 0 0 8 mA 8mA 0 1 8 mA 12mA 1 0 12 mA 8mA 1 1 12 mA 12mA What is this? Well.. 2.2. DRAM Interface Name Type Description MA[11:2] O Memory Address: This is the row and column address 3V for DRAM. These buffers include programmable size selection. MAA[1:0] O Memory Address Copy A: One copy of the MAs that 3V change during a burst read or write of DRAM. These buffers include programmable size selection. MAB[1:0] O Memory Address Copy B: A second copy of the MAs 3V that change during a burst read or write of DRAM. These buffers include programmable size selection. MWE# O Memory Write Enable. MWE# should be used as the 3V write enable for the memory data bus. This signal has a programmable size selection (see DRAMEC[MAD] field). > Apparently this document describes a method for increasing the > current flow to DRAM (programatically) because as you put more > chips into an Intel 430HX motherboard (probably any motherboard), the > current flow drops, moving the trigger level (I had a nice little > diagram drawn for me which would be tricky to duplicate here :-) ). > This makes some sense to me (even with my poor technical knowledge) > as the 4x64MB chips we are using are quite large. Reducing the DRAM > timing to 70ns will also help, although, as you say, isn't suitable. > > If anyone does add some code for this, I would be most interested in > testing it. I will try myself (when I can get the datasheet), but > my programming skills are not good, so don't rely on me. :-) If I knew jack diddly about how to do this, I would. Failing that, I am providing this data in the hopes that some more enterprising hacker who has a clue about this sort of stuff can figure it out. However, it really seems to me like this should be a BIOS configuration option, because by the time you are loading a UNIX kernel it may already be too late to try to adjust these settings. Therefore I am cc:'ing this to ASUS Tech Support as well.. I would love to see this added as an option to all Triton-II motherboard BIOS'es. It is clearly an unusual problem, you don't see it until you have LOTS of memory. :-( ... Joe ------------------------------------------------------------------------------- Joe Greco - Systems Administrator jgreco@ns.sol.net Solaria Public Access UNIX - Milwaukee, WI 414/546-7968
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