Date: Sat, 15 Feb 2025 13:10:33 +0900 (JST) From: Mori Hiroki <yamori813@yahoo.co.jp> To: "freebsd-mips@freebsd.org" <freebsd-mips@freebsd.org> Subject: Re: SMP and clock Message-ID: <1031925632.713213.1739592633864@mail.yahoo.co.jp> In-Reply-To: <981752496.606771.1739319005451@mail.yahoo.co.jp> References: <981752496.606771.1739319005451.ref@mail.yahoo.co.jp> <981752496.606771.1739319005451@mail.yahoo.co.jp>
next in thread | previous in thread | raw e-mail | index | archive | help
Hi This is my misunderstanding. Every core get self CP0 timer compare interrup= t. I found this log. https://dmesgd.nycbug.org/index.cgi?do=3Dview&id=3D3842 This kernel have other timecounter. I also make timecounter by soc timer. I have fixed problem. I seem timcounter in tick.c is not compatible SMP. Hiroki Mori > ----- Original Message ----- >=20 > From: "=E3=82=84 =E3=82=82=E3=82=8A" <yamori813@yahoo.co.jp> > To: "freebsd-mips@freebsd.org" <freebsd-mips@freebsd.org> > Date: 2025/02/12 =E6=B0=B4 09:10 > Subject: SMP and clock >=20 >=20 > Hi >=20 > I try SMP on Mediatek MT7621. >=20 > This SOC is 1004K core and 4 thread. Interrupt controller is GIC. >=20 > This SOC is MIPS clock interrupt only get core0. >=20 > I seem FreeBSD SMP support need clock interrupt every core. >=20 > How do I implement SMP on this SOC ? >=20 > Thanks >=20 > Hiroki Mori >=20 >=20 >=20
Want to link to this message? Use this URL: <https://mail-archive.FreeBSD.org/cgi/mid.cgi?1031925632.713213.1739592633864>