From owner-svn-src-head@freebsd.org Wed Sep 23 01:49:37 2020 Return-Path: Delivered-To: svn-src-head@mailman.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.nyi.freebsd.org (Postfix) with ESMTP id DF20B3E8AFF; Wed, 23 Sep 2020 01:49:37 +0000 (UTC) (envelope-from bdragon@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 4Bx1M55Tt5z44Cg; Wed, 23 Sep 2020 01:49:37 +0000 (UTC) (envelope-from bdragon@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 9FB0E9004; Wed, 23 Sep 2020 01:49:37 +0000 (UTC) (envelope-from bdragon@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id 08N1nbb5078879; Wed, 23 Sep 2020 01:49:37 GMT (envelope-from bdragon@FreeBSD.org) Received: (from bdragon@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id 08N1nbXP078877; Wed, 23 Sep 2020 01:49:37 GMT (envelope-from bdragon@FreeBSD.org) Message-Id: <202009230149.08N1nbXP078877@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: bdragon set sender to bdragon@FreeBSD.org using -f From: Brandon Bergren Date: Wed, 23 Sep 2020 01:49:37 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r366049 - head/sys/powerpc/powernv X-SVN-Group: head X-SVN-Commit-Author: bdragon X-SVN-Commit-Paths: head/sys/powerpc/powernv X-SVN-Commit-Revision: 366049 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.33 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 23 Sep 2020 01:49:37 -0000 Author: bdragon Date: Wed Sep 23 01:49:37 2020 New Revision: 366049 URL: https://svnweb.freebsd.org/changeset/base/366049 Log: [PowerPC64LE] Get XIVE up and running. More endian conversion. * Install TCEs correctly (i.e. in big endian) * Convert to big endian and back when setting up queue pages and IRQs. Sponsored by: Tag1 Consulting, Inc. Modified: head/sys/powerpc/powernv/opal_pci.c head/sys/powerpc/powernv/xive.c Modified: head/sys/powerpc/powernv/opal_pci.c ============================================================================== --- head/sys/powerpc/powernv/opal_pci.c Wed Sep 23 01:41:51 2020 (r366048) +++ head/sys/powerpc/powernv/opal_pci.c Wed Sep 23 01:49:37 2020 (r366049) @@ -385,7 +385,7 @@ opalpci_attach(device_t dev) (uintmax_t)sc->phb_id); for (i = 0; i < entries; i++) - sc->tce[i] = (i * tce_size) | OPAL_PCI_TCE_R | OPAL_PCI_TCE_W; + sc->tce[i] = htobe64((i * tce_size) | OPAL_PCI_TCE_R | OPAL_PCI_TCE_W); /* Map TCE for every PE. It seems necessary for Power8 */ for (i = 0; i < npe; i++) { Modified: head/sys/powerpc/powernv/xive.c ============================================================================== --- head/sys/powerpc/powernv/xive.c Wed Sep 23 01:41:51 2020 (r366048) +++ head/sys/powerpc/powernv/xive.c Wed Sep 23 01:49:37 2020 (r366049) @@ -377,6 +377,9 @@ xive_attach(device_t dev) opal_call(OPAL_XIVE_GET_VP_INFO, xive_cpud->vp, NULL, vtophys(&xive_cpud->cam), NULL, vtophys(&xive_cpud->chip)); + xive_cpud->cam = be64toh(xive_cpud->cam); + xive_cpud->chip = be64toh(xive_cpud->chip); + /* Allocate the queue page and populate the queue state data. */ xive_cpud->queue.q_page = contigmalloc(PAGE_SIZE, M_XIVE, M_ZERO | M_WAITOK, 0, BUS_SPACE_MAXADDR, PAGE_SIZE, 0); @@ -707,6 +710,12 @@ xive_init_irq(struct xive_irq *irqd, u_int irq) vtophys(&trig_phys), vtophys(&esb_shift), vtophys(&irqd->chip)); + irqd->flags = be64toh(irqd->flags); + eoi_phys = be64toh(eoi_phys); + trig_phys = be64toh(trig_phys); + esb_shift = be32toh(esb_shift); + irqd->chip = be32toh(irqd->chip); + irqd->girq = irq; irqd->esb_size = 1 << esb_shift; irqd->eoi_page = (vm_offset_t)pmap_mapdev(eoi_phys, irqd->esb_size); @@ -721,6 +730,10 @@ xive_init_irq(struct xive_irq *irqd, u_int irq) opal_call(OPAL_XIVE_GET_IRQ_CONFIG, irq, vtophys(&irqd->vp), vtophys(&irqd->prio), vtophys(&irqd->lirq)); + + irqd->vp = be64toh(irqd->vp); + irqd->prio = be64toh(irqd->prio); + irqd->lirq = be32toh(irqd->lirq); } /* Allocate an IRQ struct before populating it. */