From owner-svn-src-projects@FreeBSD.ORG Sat Nov 2 19:14:23 2013 Return-Path: Delivered-To: svn-src-projects@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [8.8.178.115]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTP id 7D375BA1; Sat, 2 Nov 2013 19:14:23 +0000 (UTC) (envelope-from marcel@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.freebsd.org (Postfix) with ESMTPS id 50DBE2400; Sat, 2 Nov 2013 19:14:23 +0000 (UTC) Received: from svn.freebsd.org ([127.0.1.70]) by svn.freebsd.org (8.14.7/8.14.7) with ESMTP id rA2JEMpD006846; Sat, 2 Nov 2013 19:14:22 GMT (envelope-from marcel@svn.freebsd.org) Received: (from marcel@localhost) by svn.freebsd.org (8.14.7/8.14.5/Submit) id rA2JEMEi006845; Sat, 2 Nov 2013 19:14:22 GMT (envelope-from marcel@svn.freebsd.org) Message-Id: <201311021914.rA2JEMEi006845@svn.freebsd.org> From: Marcel Moolenaar Date: Sat, 2 Nov 2013 19:14:22 +0000 (UTC) To: src-committers@freebsd.org, svn-src-projects@freebsd.org Subject: svn commit: r257553 - projects/altix2/sys/ia64/sgisn X-SVN-Group: projects MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-projects@freebsd.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: "SVN commit messages for the src " projects" tree" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 02 Nov 2013 19:14:23 -0000 Author: marcel Date: Sat Nov 2 19:14:22 2013 New Revision: 257553 URL: http://svnweb.freebsd.org/changeset/base/257553 Log: 1. Assign shub_dev only for domain 0. The whole thing is wrong anyway. What we need is affinity between CPUs and Shub ASICs so that we can have the per-CPU structure hold the pointer to the SHub device that CPU is connected to. With that, we then need to bind interrupts only to CPUs within the same node and ll will be fine. This change merely makes domain 0 work all the time, which gives us a more reliable baseline for running natively while adding nodes. 2. Cast sc->sc_nasid to a 64-bit type before we shift the value left by more than 32 bits. Without that the memory mapped I/O address would always be targeting the SHub with NASID 0. 3. Create the RTC device when we create the SN console device. No need to make it a separate conditional that effectively ends up doing the same thing. Modified: projects/altix2/sys/ia64/sgisn/sgisn_shub.c Modified: projects/altix2/sys/ia64/sgisn/sgisn_shub.c ============================================================================== --- projects/altix2/sys/ia64/sgisn/sgisn_shub.c Sat Nov 2 18:40:18 2013 (r257552) +++ projects/altix2/sys/ia64/sgisn/sgisn_shub.c Sat Nov 2 19:14:22 2013 (r257553) @@ -385,7 +385,8 @@ sgisn_shub_attach(device_t dev) sc->sc_dev = dev; sc->sc_domain = device_get_unit(dev); - shub_dev = dev; + if (sc->sc_domain == 0) + shub_dev = dev; /* * Get the physical memory region that is connected to the MD I/F @@ -416,7 +417,7 @@ sgisn_shub_attach(device_t dev) sc->sc_nasid = (sc->sc_membase >> sc->sc_nasid_shft) & sc->sc_nasid_mask; - sc->sc_mmraddr = (sc->sc_nasid << sc->sc_nasid_shft) | + sc->sc_mmraddr = ((vm_paddr_t)sc->sc_nasid << sc->sc_nasid_shft) | (((sc->sc_hubtype == 0) ? 9UL : 3UL) << 32); sc->sc_tag = IA64_BUS_SPACE_MEM; bus_space_map(sc->sc_tag, sc->sc_mmraddr, 1UL << 32, 0, &sc->sc_hndl); @@ -447,14 +448,12 @@ sgisn_shub_attach(device_t dev) for (wdgt = 0; wdgt < SGISN_HUB_NWIDGETS; wdgt++) sc->sc_fwhub->hub_widget[wdgt].wgt_hub = sc->sc_fwhub; - /* Create a child for the SAL-based console. */ + /* Create a child for the SAL-based console and the RTC. */ r = ia64_sal_entry(SAL_SGISN_MASTER_NASID, 0, 0, 0, 0, 0, 0, 0); if (r.sal_status == 0 && r.sal_result[0] == sc->sc_nasid) { child = device_add_child(dev, "sncon", -1); device_set_ivars(child, (void *)(uintptr_t)~0UL); - } - if (sc->sc_nasid == 0) { /* Use the SHub's RTC as a time counter. */ r = ia64_sal_entry(SAL_FREQ_BASE, 2, 0, 0, 0, 0, 0, 0); if (r.sal_status == 0) {