From owner-freebsd-mips@FreeBSD.ORG Thu Aug 23 23:48:51 2012 Return-Path: Delivered-To: freebsd-mips@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 76D75106564A; Thu, 23 Aug 2012 23:48:51 +0000 (UTC) (envelope-from adrian.chadd@gmail.com) Received: from mail-pb0-f54.google.com (mail-pb0-f54.google.com [209.85.160.54]) by mx1.freebsd.org (Postfix) with ESMTP id 39D918FC17; Thu, 23 Aug 2012 23:48:50 +0000 (UTC) Received: by pbbrp2 with SMTP id rp2so2428732pbb.13 for ; Thu, 23 Aug 2012 16:48:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:sender:in-reply-to:references:date :x-google-sender-auth:message-id:subject:from:to:cc:content-type; bh=Mskt1FyQ/HqkFMIEUCOxaM1D7q7pn1393qcB/jAWPnU=; b=Cog3Xq8zSN5Zl7K2a0nXw/INEb20LCEzMNo7+vVAij2/aBmAPh+3U/OeBe74m0dmGu yAdtXDFPqSEqFCe8mcV593Etog3zCrMHGhF47i0iRyX9oV1gNY2rd0uKCrujMR0lghrE xoLWOYXbxIsljKOc7nRsv7VN8fykkPqlryniKOtsuUZIOnQlNS90mNOdbLPIm/EuaavE AhpgCjau9GHafS+R1SB4v3+8ZVMYaMvawTyITBPJqGICI01PtxMnkSh2codWZU5+ffbF RfElqIHdkf2EoS0iy0+zJi5plfdvMjcWRuhux+m1H+QFy7lNg/SAFMIFedzmPkv8L79C IqOw== MIME-Version: 1.0 Received: by 10.68.231.233 with SMTP id tj9mr8442260pbc.39.1345765730704; Thu, 23 Aug 2012 16:48:50 -0700 (PDT) Sender: adrian.chadd@gmail.com Received: by 10.68.36.106 with HTTP; Thu, 23 Aug 2012 16:48:50 -0700 (PDT) In-Reply-To: <1345765503.27688.602.camel@revolution.hippie.lan> References: <1345757300.27688.535.camel@revolution.hippie.lan> <3A08EB08-2BBF-4B0F-97F2-A3264754C4B7@bsdimp.com> <1345763393.27688.578.camel@revolution.hippie.lan> <1345765503.27688.602.camel@revolution.hippie.lan> Date: Thu, 23 Aug 2012 16:48:50 -0700 X-Google-Sender-Auth: xNYhy3PgvZjcI4uwRsLgaOc5SX4 Message-ID: From: Adrian Chadd To: Ian Lepore Content-Type: text/plain; charset=ISO-8859-1 Cc: freebsd-arm@freebsd.org, freebsd-mips@freebsd.org, freebsd-arch@freebsd.org Subject: Re: Partial cacheline flush problems on ARM and MIPS X-BeenThere: freebsd-mips@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Porting FreeBSD to MIPS List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 23 Aug 2012 23:48:51 -0000 On 23 August 2012 16:45, Ian Lepore wrote: > So do you think it's safe to assume that any given dma tag that has an > alignment constraint also implicitly has a buffer size constraint that > the size must be a multiple of the alignment? > > What if we have a platform with a 32-byte cacheline / DMA granularity, > and then we have a builtin device on that SoC which can only do DMA on a > 64K alignment (which its tag would reflect), but the hardware can move > as little as 1 byte at a time? Children of that bridge device come > along and allocate little 16-byte buffers that eat 16 pages each. It > doesn't seem all that far-fetched to me. That hardware would suck, wouldn't it? In what case though would the hardware say it can only DMA on a 64k alignment BUT move one byte at a time? Then what would the starting address be for each DMA? adrian