From owner-svn-src-head@freebsd.org Wed Nov 1 02:40:17 2017 Return-Path: Delivered-To: svn-src-head@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 087A4E4B7D9; Wed, 1 Nov 2017 02:40:17 +0000 (UTC) (envelope-from jhibbits@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id C9B066DCD0; Wed, 1 Nov 2017 02:40:16 +0000 (UTC) (envelope-from jhibbits@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id vA12eFmN051094; Wed, 1 Nov 2017 02:40:15 GMT (envelope-from jhibbits@FreeBSD.org) Received: (from jhibbits@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id vA12eFqX051092; Wed, 1 Nov 2017 02:40:15 GMT (envelope-from jhibbits@FreeBSD.org) Message-Id: <201711010240.vA12eFqX051092@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: jhibbits set sender to jhibbits@FreeBSD.org using -f From: Justin Hibbits Date: Wed, 1 Nov 2017 02:40:15 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r325258 - head/sys/powerpc/booke X-SVN-Group: head X-SVN-Commit-Author: jhibbits X-SVN-Commit-Paths: head/sys/powerpc/booke X-SVN-Commit-Revision: 325258 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 01 Nov 2017 02:40:17 -0000 Author: jhibbits Date: Wed Nov 1 02:40:15 2017 New Revision: 325258 URL: https://svnweb.freebsd.org/changeset/base/325258 Log: Fix debug interrupts on 64-bit Book-E Use a WORD_SIZE macro to define the correct offset to the second word needed. This corrects the offset calculation in 64-bit builds. Modified: head/sys/powerpc/booke/locore.S head/sys/powerpc/booke/trap_subr.S Modified: head/sys/powerpc/booke/locore.S ============================================================================== --- head/sys/powerpc/booke/locore.S Wed Nov 1 01:22:33 2017 (r325257) +++ head/sys/powerpc/booke/locore.S Wed Nov 1 02:40:15 2017 (r325258) @@ -57,6 +57,7 @@ #define THREAD_REG %r13 #define ADDR(x) \ .llong x +#define WORD_SIZE 8 #else #define GET_TOCBASE(r) #define TOC_RESTORE @@ -72,6 +73,7 @@ #define THREAD_REG %r2 #define ADDR(x) \ .long x +#define WORD_SIZE 4 #endif .text Modified: head/sys/powerpc/booke/trap_subr.S ============================================================================== --- head/sys/powerpc/booke/trap_subr.S Wed Nov 1 01:22:33 2017 (r325257) +++ head/sys/powerpc/booke/trap_subr.S Wed Nov 1 02:40:15 2017 (r325258) @@ -970,19 +970,14 @@ int_debug_int: GET_CPUINFO(%r3) LOAD %r3, (PC_BOOKE_CRITSAVE+CPUSAVE_SRR0)(%r3) bl 0f -#ifdef __powerpc64__ - .llong interrupt_vector_base-. - .llong interrupt_vector_top-. -#else - .long interrupt_vector_base-. - .long interrupt_vector_top-. -#endif + ADDR(interrupt_vector_base-.) + ADDR(interrupt_vector_top-.) 0: mflr %r5 LOAD %r4,0(%r5) /* interrupt_vector_base in r4 */ add %r4,%r4,%r5 CMPL cr0, %r3, %r4 blt trap_common - LOAD %r4,4(%r5) /* interrupt_vector_top in r4 */ + LOAD %r4,WORD_SIZE(%r5) /* interrupt_vector_top in r4 */ add %r4,%r4,%r5 addi %r4,%r4,4 CMPL cr0, %r3, %r4