From owner-svn-src-all@FreeBSD.ORG Wed Nov 14 12:11:24 2012 Return-Path: Delivered-To: svn-src-all@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [69.147.83.52]) by hub.freebsd.org (Postfix) with ESMTP id 7B395E7D; Wed, 14 Nov 2012 12:11:24 +0000 (UTC) (envelope-from cognet@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) by mx1.freebsd.org (Postfix) with ESMTP id 60C3B8FC16; Wed, 14 Nov 2012 12:11:24 +0000 (UTC) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.5/8.14.5) with ESMTP id qAECBODK068699; Wed, 14 Nov 2012 12:11:24 GMT (envelope-from cognet@svn.freebsd.org) Received: (from cognet@localhost) by svn.freebsd.org (8.14.5/8.14.5/Submit) id qAECBO5q068698; Wed, 14 Nov 2012 12:11:24 GMT (envelope-from cognet@svn.freebsd.org) Message-Id: <201211141211.qAECBO5q068698@svn.freebsd.org> From: Olivier Houchard Date: Wed, 14 Nov 2012 12:11:24 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r243026 - head/sys/arm/arm X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 14 Nov 2012 12:11:24 -0000 Author: cognet Date: Wed Nov 14 12:11:23 2012 New Revision: 243026 URL: http://svnweb.freebsd.org/changeset/base/243026 Log: Make it clear the L2 ops are filled for any cpu using a PL310 cache, not just the omap4. Spotted out by: Giovanni Trematerra Modified: head/sys/arm/arm/cpufunc.c Modified: head/sys/arm/arm/cpufunc.c ============================================================================== --- head/sys/arm/arm/cpufunc.c Wed Nov 14 11:05:16 2012 (r243025) +++ head/sys/arm/arm/cpufunc.c Wed Nov 14 12:11:23 2012 (r243026) @@ -1067,7 +1067,8 @@ struct cpu_functions cortexa_cpufuncs = armv7_idcache_wbinv_all, /* idcache_wbinv_all */ armv7_idcache_wbinv_range, /* idcache_wbinv_range */ - /* Note: From OMAP4 the L2 ops are filled in when the + /* + * Note: For CPUs using the PL310 the L2 ops are filled in when the * L2 cache controller is actually enabled. */ cpufunc_nullop, /* l2cache_wbinv_all */