9mf45+W/wJ4tfSNo4/ ves0rJ3A0spxxpykHGuf2Pz9JAO1QLw15UG6ITnXkl962PunrKaAcUqc/i4KccPseCJQCT KprLKu4j3lQRxjdTEDO1d3nqew784nTrWSJvCO1Q4KDrRmNj9KLkthIdFMcI6gFB7YEMGT rB6xWNdHTqe+CRywJMrfqq4YdOd+XJJaFFtl8HeKfieudvJnFZ9bKCYs7CAXae3xbuuCEz UhHhTruHH06d3oOqcYwFV4eSwpab8W9rKyaBxOFghvX3MwCygyjSvSHJSW+1AQ== ARC-Authentication-Results: i=1; mx1.freebsd.org; none ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1777402167; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=QpPCI2YesGLOb4EvlfqFHNPwvXVvfZrRjFtNTawuVEI=; b=yyjCXaQRz5ir/a87SyUW2GMKf2zxX3pbHmdHWsmFIZjMk/+3fSZ2CUeb2bKz/j/0cAl2Kq TFh5LX++qZwGPOjDmfIOFTkZxSw6+cShC+OjnprzKNpzS4ifuuhBN7oosBi9EQhrICPp+k CQwvFrK2296/7uNJ6RymuZGKrsbZ7bIyLeGKvHRHnRPrB+5T0jVQvnh54Hy+WwoFo/lE6o 8NS0jPFHCWJ8E6g9Gyc2lSfDRpQ/RUxwaSDnF0r62aSuDIzlowcXOBOPAVtXzH3Nz6tUNM aTibWCMxjZ+FON5KC6/H5t19yAH/dt3JkaJYCMGeQOpW0KS+nXeFG0MrX6DgQg== Received: from gitrepo.freebsd.org (gitrepo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:5]) by mxrelay.nyi.freebsd.org (Postfix) with ESMTP id 4g4qGv35bQz15Rs for ; Tue, 28 Apr 2026 18:49:27 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from git (uid 1279) (envelope-from git@FreeBSD.org) id 24947 by gitrepo.freebsd.org (DragonFly Mail Agent v0.13+ on gitrepo.freebsd.org); Tue, 28 Apr 2026 18:49:27 +0000 To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-main@FreeBSD.org Cc: Andre Silva From: Mitchell Horne Subject: git: 146b30bad9f6 - main - hwpmc: Add extra_mask sysctls per counter type List-Id: Commit messages for all branches of the src repository List-Archive: https://lists.freebsd.org/archives/dev-commits-src-all List-Help: List-Post: List-Subscribe: List-Unsubscribe: X-BeenThere: dev-commits-src-all@freebsd.org Sender: owner-dev-commits-src-all@FreeBSD.org MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Git-Committer: mhorne X-Git-Repository: src X-Git-Refname: refs/heads/main X-Git-Reftype: branch X-Git-Commit: 146b30bad9f65a098e6c09ae93bb1da2ff59616d Auto-Submitted: auto-generated Date: Tue, 28 Apr 2026 18:49:27 +0000 Message-Id: <69f10137.24947.5c65a2ab@gitrepo.freebsd.org> The branch main has been updated by mhorne: URL: https://cgit.FreeBSD.org/src/commit/?id=146b30bad9f65a098e6c09ae93bb1da2ff59616d commit 146b30bad9f65a098e6c09ae93bb1da2ff59616d Author: Andre Silva AuthorDate: 2026-04-23 19:27:06 +0000 Commit: Mitchell Horne CommitDate: 2026-04-28 18:49:22 +0000 hwpmc: Add extra_mask sysctls per counter type Expose kern.hwpmc.{ibs_fetch,ibs_op,amd_core,amd_l3,amd_df}_extra_mask as RWTUN uint64s that OR into the CPUID-derived allow mask at validation time. Default 0, so the strict policy applies unless an administrator opts bits back in — intended for testing the wrmsr_safe path in PR #2157. Reviewed by: mhorne, Ali Mashtizadeh Sponsored by: AMD Signed-off-by: Andre Silva Pull Request: https://github.com/freebsd/freebsd-src/pull/2140 --- sys/dev/hwpmc/hwpmc_amd.c | 25 ++++++++++++++++++++++--- sys/dev/hwpmc/hwpmc_ibs.c | 18 +++++++++++++++++- 2 files changed, 39 insertions(+), 4 deletions(-) diff --git a/sys/dev/hwpmc/hwpmc_amd.c b/sys/dev/hwpmc/hwpmc_amd.c index 8531db13dc6f..299021494716 100644 --- a/sys/dev/hwpmc/hwpmc_amd.c +++ b/sys/dev/hwpmc/hwpmc_amd.c @@ -40,6 +40,7 @@ #include #include #include +#include #include #include @@ -183,6 +184,24 @@ static uint64_t amd_core_allowed_mask; static uint64_t amd_l3_allowed_mask; static uint64_t amd_df_allowed_mask; +static uint64_t amd_core_extra_mask; +static uint64_t amd_l3_extra_mask; +static uint64_t amd_df_extra_mask; + +SYSCTL_DECL(_kern_hwpmc); + +SYSCTL_U64(_kern_hwpmc, OID_AUTO, amd_core_extra_mask, CTLFLAG_RDTUN, + &amd_core_extra_mask, 0, + "Extra allowed bits in AMD core PMU PERFEVTSEL (override; default 0)"); + +SYSCTL_U64(_kern_hwpmc, OID_AUTO, amd_l3_extra_mask, CTLFLAG_RDTUN, + &amd_l3_extra_mask, 0, + "Extra allowed bits in AMD L3 PMU control (override; default 0)"); + +SYSCTL_U64(_kern_hwpmc, OID_AUTO, amd_df_extra_mask, CTLFLAG_RDTUN, + &amd_df_extra_mask, 0, + "Extra allowed bits in AMD DF PMU control (override; default 0)"); + static void amd_init_policy(void) { @@ -205,13 +224,13 @@ amd_config_mask(enum sub_class subclass, uint64_t caps) switch (subclass) { case PMC_AMD_SUB_CLASS_CORE: - return (amd_core_allowed_mask | + return (amd_core_allowed_mask | amd_core_extra_mask | (((caps & PMC_CAP_PRECISE) != 0) ? AMD_PMC_PRECISERETIRE : 0)); case PMC_AMD_SUB_CLASS_L3_CACHE: - return (amd_l3_allowed_mask); + return (amd_l3_allowed_mask | amd_l3_extra_mask); case PMC_AMD_SUB_CLASS_DATA_FABRIC: - return (amd_df_allowed_mask); + return (amd_df_allowed_mask | amd_df_extra_mask); default: return (0); } diff --git a/sys/dev/hwpmc/hwpmc_ibs.c b/sys/dev/hwpmc/hwpmc_ibs.c index 93e43d657633..8cfe7b2df145 100644 --- a/sys/dev/hwpmc/hwpmc_ibs.c +++ b/sys/dev/hwpmc/hwpmc_ibs.c @@ -36,6 +36,7 @@ #include #include #include +#include #include #define EXTERR_CATEGORY EXTERR_CAT_HWPMC_IBS @@ -60,6 +61,19 @@ static uint64_t ibs_features; static uint64_t ibs_fetch_allowed_mask; static uint64_t ibs_op_allowed_mask; +static uint64_t ibs_fetch_extra_mask; +static uint64_t ibs_op_extra_mask; + +SYSCTL_DECL(_kern_hwpmc); + +SYSCTL_U64(_kern_hwpmc, OID_AUTO, ibs_fetch_extra_mask, CTLFLAG_RDTUN, + &ibs_fetch_extra_mask, 0, + "Extra allowed bits in the IBS fetch control MSR (override; default 0)"); + +SYSCTL_U64(_kern_hwpmc, OID_AUTO, ibs_op_extra_mask, CTLFLAG_RDTUN, + &ibs_op_extra_mask, 0, + "Extra allowed bits in the IBS op control MSR (override; default 0)"); + /* * Per-processor information */ @@ -98,7 +112,7 @@ static int ibs_validate_fetch_config(uint64_t config) { - if ((config & ~ibs_fetch_allowed_mask) != 0) + if ((config & ~(ibs_fetch_allowed_mask | ibs_fetch_extra_mask)) != 0) return (EINVAL); return (0); @@ -120,6 +134,8 @@ ibs_validate_op_config(uint64_t config) allowed_mask |= IBS_OP_CTL_LDLATMASK | IBS_OP_CTL_L3MISSONLY; } + allowed_mask |= ibs_op_extra_mask; + if ((config & ~allowed_mask) != 0) return (EINVAL);