From owner-cvs-all@FreeBSD.ORG Tue Feb 22 19:03:07 2005 Return-Path: Delivered-To: cvs-all@freebsd.org Received: from mx1.FreeBSD.org (mx1.freebsd.org [216.136.204.125]) by hub.freebsd.org (Postfix) with ESMTP id 5168B16A4CE; Tue, 22 Feb 2005 19:03:07 +0000 (GMT) Received: from www.cryptography.com (li-22.members.linode.com [64.5.53.22]) by mx1.FreeBSD.org (Postfix) with ESMTP id 0AC9843D2D; Tue, 22 Feb 2005 19:03:07 +0000 (GMT) (envelope-from nate@root.org) Received: from [10.0.0.34] (adsl-67-119-74-222.dsl.sntc01.pacbell.net [67.119.74.222]) by www.cryptography.com (8.12.8/8.12.8) with ESMTP id j1MJ34Zj014234 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NOT); Tue, 22 Feb 2005 11:03:05 -0800 Message-ID: <421B81E4.6080909@root.org> Date: Tue, 22 Feb 2005 11:03:00 -0800 From: Nate Lawson User-Agent: Mozilla Thunderbird 0.9 (Windows/20041103) X-Accept-Language: en-us, en MIME-Version: 1.0 To: David Schultz References: <200502211604.j1LG4NNx037623@repoman.freebsd.org> <421B24E2.7050800@portaone.com> <20050222135251.GB29054@VARK.MIT.EDU> In-Reply-To: <20050222135251.GB29054@VARK.MIT.EDU> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit cc: cvs-src@FreeBSD.ORG cc: Maxim Sobolev cc: src-committers@FreeBSD.ORG cc: cvs-all@FreeBSD.ORG Subject: Re: cvs commit: src/lib/msun/i387 Makefile.inc e_atan2.S e_atan2f.S s_atan.S X-BeenThere: cvs-all@freebsd.org X-Mailman-Version: 2.1.1 Precedence: list List-Id: CVS commit messages for the entire tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 22 Feb 2005 19:03:07 -0000 David Schultz wrote: > By the way, here are some other results for the Pentium 4, all > without SSE. SSE makes things a bit worse, probably because the > x87 and SSE registers are shared, and the Pentium 4 imposes a > large penalty for switching between the two sets. I don't believe this is correct. MMX and x87 use the same register context (hence emms), however the XMM registers (SSE*) are separate. It's possible gcc is generating MMX instructions though with your SSE command line switch. -- Nate