From owner-svn-src-head@freebsd.org Fri Apr 14 20:15:18 2017 Return-Path: Delivered-To: svn-src-head@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id C9447D3A00A; Fri, 14 Apr 2017 20:15:18 +0000 (UTC) (envelope-from np@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 8A496DEB; Fri, 14 Apr 2017 20:15:18 +0000 (UTC) (envelope-from np@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id v3EKFH3u017570; Fri, 14 Apr 2017 20:15:17 GMT (envelope-from np@FreeBSD.org) Received: (from np@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id v3EKFHrT017566; Fri, 14 Apr 2017 20:15:17 GMT (envelope-from np@FreeBSD.org) Message-Id: <201704142015.v3EKFHrT017566@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: np set sender to np@FreeBSD.org using -f From: Navdeep Parhar Date: Fri, 14 Apr 2017 20:15:17 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r316940 - head/sys/dev/cxgbe/iw_cxgbe X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 14 Apr 2017 20:15:18 -0000 Author: np Date: Fri Apr 14 20:15:17 2017 New Revision: 316940 URL: https://svnweb.freebsd.org/changeset/base/316940 Log: cxgbe/iw_cxgbe: Report the actual values of various parameters as configured by the firmware. MFC after: 3 days Sponsored by: Chelsio Communications Modified: head/sys/dev/cxgbe/iw_cxgbe/provider.c head/sys/dev/cxgbe/iw_cxgbe/qp.c head/sys/dev/cxgbe/iw_cxgbe/t4.h Modified: head/sys/dev/cxgbe/iw_cxgbe/provider.c ============================================================================== --- head/sys/dev/cxgbe/iw_cxgbe/provider.c Fri Apr 14 20:10:18 2017 (r316939) +++ head/sys/dev/cxgbe/iw_cxgbe/provider.c Fri Apr 14 20:15:17 2017 (r316940) @@ -307,6 +307,7 @@ c4iw_query_device(struct ib_device *ibde { struct c4iw_dev *dev = to_c4iw_dev(ibdev); struct adapter *sc = dev->rdev.adap; + const int spg_ndesc = sc->params.sge.spg_len / EQ_ESIZE; CTR3(KTR_IW_CXGBE, "%s ibdev %p, props %p", __func__, ibdev, props); @@ -320,13 +321,15 @@ c4iw_query_device(struct ib_device *ibde props->vendor_id = pci_get_vendor(sc->dev); props->vendor_part_id = pci_get_device(sc->dev); props->max_mr_size = T4_MAX_MR_SIZE; - props->max_qp = T4_MAX_NUM_QP; - props->max_qp_wr = T4_MAX_QP_DEPTH; + props->max_qp = sc->vres.qp.size / 2; + props->max_qp_wr = T4_MAX_QP_DEPTH(spg_ndesc); props->max_sge = T4_MAX_RECV_SGE; props->max_sge_rd = 1; - props->max_qp_rd_atom = c4iw_max_read_depth; - props->max_qp_init_rd_atom = c4iw_max_read_depth; - props->max_cq = T4_MAX_NUM_CQ; + props->max_res_rd_atom = sc->params.max_ird_adapter; + props->max_qp_rd_atom = min(sc->params.max_ordird_qp, + c4iw_max_read_depth); + props->max_qp_init_rd_atom = props->max_qp_rd_atom; + props->max_cq = sc->vres.qp.size; props->max_cqe = T4_MAX_CQ_DEPTH; props->max_mr = c4iw_num_stags(&dev->rdev); props->max_pd = T4_MAX_NUM_PD; Modified: head/sys/dev/cxgbe/iw_cxgbe/qp.c ============================================================================== --- head/sys/dev/cxgbe/iw_cxgbe/qp.c Fri Apr 14 20:10:18 2017 (r316939) +++ head/sys/dev/cxgbe/iw_cxgbe/qp.c Fri Apr 14 20:15:17 2017 (r316940) @@ -133,6 +133,7 @@ static int create_qp(struct c4iw_rdev *r int ret; int eqsize; struct wrqe *wr; + const int spg_ndesc = sc->params.sge.spg_len / EQ_ESIZE; wq->sq.qid = c4iw_get_qpid(rdev, uctx); if (!wq->sq.qid) @@ -214,8 +215,7 @@ static int create_qp(struct c4iw_rdev *r res->u.sqrq.op = FW_RI_RES_OP_WRITE; /* eqsize is the number of 64B entries plus the status page size. */ - eqsize = wq->sq.size * T4_SQ_NUM_SLOTS + - (sc->params.sge.spg_len / EQ_ESIZE); + eqsize = wq->sq.size * T4_SQ_NUM_SLOTS + spg_ndesc; res->u.sqrq.fetchszm_to_iqid = cpu_to_be32( V_FW_RI_RES_WR_HOSTFCMODE(0) | /* no host cidx updates */ @@ -237,8 +237,7 @@ static int create_qp(struct c4iw_rdev *r res->u.sqrq.op = FW_RI_RES_OP_WRITE; /* eqsize is the number of 64B entries plus the status page size. */ - eqsize = wq->rq.size * T4_RQ_NUM_SLOTS + - (sc->params.sge.spg_len / EQ_ESIZE); + eqsize = wq->rq.size * T4_RQ_NUM_SLOTS + spg_ndesc; res->u.sqrq.fetchszm_to_iqid = cpu_to_be32( V_FW_RI_RES_WR_HOSTFCMODE(0) | /* no host cidx updates */ V_FW_RI_RES_WR_CPRIO(0) | /* don't keep in chip cache */ @@ -1523,7 +1522,7 @@ c4iw_create_qp(struct ib_pd *pd, struct struct c4iw_create_qp_resp uresp; int sqsize, rqsize; struct c4iw_ucontext *ucontext; - int ret; + int ret, spg_ndesc; struct c4iw_mm_entry *mm1, *mm2, *mm3, *mm4; CTR2(KTR_IW_CXGBE, "%s ib_pd %p", __func__, pd); @@ -1541,12 +1540,13 @@ c4iw_create_qp(struct ib_pd *pd, struct if (attrs->cap.max_inline_data > T4_MAX_SEND_INLINE) return ERR_PTR(-EINVAL); + spg_ndesc = rhp->rdev.adap->params.sge.spg_len / EQ_ESIZE; rqsize = roundup(attrs->cap.max_recv_wr + 1, 16); - if (rqsize > T4_MAX_RQ_SIZE) + if (rqsize > T4_MAX_RQ_SIZE(spg_ndesc)) return ERR_PTR(-E2BIG); sqsize = roundup(attrs->cap.max_send_wr + 1, 16); - if (sqsize > T4_MAX_SQ_SIZE) + if (sqsize > T4_MAX_SQ_SIZE(spg_ndesc)) return ERR_PTR(-E2BIG); ucontext = pd->uobject ? to_c4iw_ucontext(pd->uobject->context) : NULL; @@ -1556,9 +1556,10 @@ c4iw_create_qp(struct ib_pd *pd, struct if (!qhp) return ERR_PTR(-ENOMEM); qhp->wq.sq.size = sqsize; - qhp->wq.sq.memsize = (sqsize + 1) * sizeof *qhp->wq.sq.queue; + qhp->wq.sq.memsize = (sqsize + spg_ndesc) * sizeof *qhp->wq.sq.queue + + 16 * sizeof(__be64); qhp->wq.rq.size = rqsize; - qhp->wq.rq.memsize = (rqsize + 1) * sizeof *qhp->wq.rq.queue; + qhp->wq.rq.memsize = (rqsize + spg_ndesc) * sizeof *qhp->wq.rq.queue; if (ucontext) { qhp->wq.sq.memsize = roundup(qhp->wq.sq.memsize, PAGE_SIZE); Modified: head/sys/dev/cxgbe/iw_cxgbe/t4.h ============================================================================== --- head/sys/dev/cxgbe/iw_cxgbe/t4.h Fri Apr 14 20:10:18 2017 (r316939) +++ head/sys/dev/cxgbe/iw_cxgbe/t4.h Fri Apr 14 20:15:17 2017 (r316940) @@ -59,21 +59,17 @@ #define CIDXINC_SHIFT 0 #define CIDXINC(x) ((x) << CIDXINC_SHIFT) -#define T4_MAX_NUM_QP (1<<16) -#define T4_MAX_NUM_CQ (1<<15) #define T4_MAX_NUM_PD 65536 -#define T4_EQ_STATUS_ENTRIES (L1_CACHE_BYTES > 64 ? 2 : 1) -#define T4_MAX_EQ_SIZE (65520 - T4_EQ_STATUS_ENTRIES) -#define T4_MAX_IQ_SIZE (65520 - 1) -#define T4_MAX_RQ_SIZE (8192 - T4_EQ_STATUS_ENTRIES) -#define T4_MAX_SQ_SIZE (T4_MAX_EQ_SIZE - 1) -#define T4_MAX_QP_DEPTH (T4_MAX_RQ_SIZE - 1) -#define T4_MAX_CQ_DEPTH (T4_MAX_IQ_SIZE - 1) +#define T4_MAX_EQ_SIZE 65520 +#define T4_MAX_IQ_SIZE 65520 +#define T4_MAX_RQ_SIZE(n) (8192 - (n) - 1) +#define T4_MAX_SQ_SIZE(n) (T4_MAX_EQ_SIZE - (n) - 1) +#define T4_MAX_QP_DEPTH(n) (T4_MAX_RQ_SIZE(n)) +#define T4_MAX_CQ_DEPTH (T4_MAX_IQ_SIZE - 2) #define T4_MAX_MR_SIZE (~0ULL - 1) #define T4_PAGESIZE_MASK 0xffffffff000 /* 4KB-8TB */ #define T4_STAG_UNSET 0xffffffff #define T4_FW_MAJ 0 -#define T4_EQ_STATUS_ENTRIES (L1_CACHE_BYTES > 64 ? 2 : 1) #define A_PCIE_MA_SYNC 0x30b4 struct t4_status_page {