From owner-dev-commits-src-main@freebsd.org Sun May 2 10:56:14 2021 Return-Path: Delivered-To: dev-commits-src-main@mailman.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.nyi.freebsd.org (Postfix) with ESMTP id B7A87621361; Sun, 2 May 2021 10:56:14 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "R3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 4FY31p4JhNz4YdZ; Sun, 2 May 2021 10:56:14 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from gitrepo.freebsd.org (gitrepo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:5]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 84C2318A7; Sun, 2 May 2021 10:56:14 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from gitrepo.freebsd.org ([127.0.1.44]) by gitrepo.freebsd.org (8.16.1/8.16.1) with ESMTP id 142AuEGs077010; Sun, 2 May 2021 10:56:14 GMT (envelope-from git@gitrepo.freebsd.org) Received: (from git@localhost) by gitrepo.freebsd.org (8.16.1/8.16.1/Submit) id 142AuEUJ077009; Sun, 2 May 2021 10:56:14 GMT (envelope-from git) Date: Sun, 2 May 2021 10:56:14 GMT Message-Id: <202105021056.142AuEUJ077009@gitrepo.freebsd.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-main@FreeBSD.org From: Andrew Turner Subject: git: 2420f6aed9e3 - main - Enable IPIs on CPU 0 on arm and arm64 MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Git-Committer: andrew X-Git-Repository: src X-Git-Refname: refs/heads/main X-Git-Reftype: branch X-Git-Commit: 2420f6aed9e355ff65377152ba977b3a5ac441d1 Auto-Submitted: auto-generated X-BeenThere: dev-commits-src-main@freebsd.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Commit messages for the main branch of the src repository List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 02 May 2021 10:56:14 -0000 The branch main has been updated by andrew: URL: https://cgit.FreeBSD.org/src/commit/?id=2420f6aed9e355ff65377152ba977b3a5ac441d1 commit 2420f6aed9e355ff65377152ba977b3a5ac441d1 Author: Andrew Turner AuthorDate: 2021-05-02 07:43:34 +0000 Commit: Andrew Turner CommitDate: 2021-05-02 07:43:34 +0000 Enable IPIs on CPU 0 on arm and arm64 Not all interrupt controllers enable IPIs by default as the Arm GIC specs make it an implementation defined option. As at least two hypervisors have also previously masked the IPIs on boot. As we already enable these IPIs on the non-boot CPUs it is expected this is a safe operation. Differential Revision: https://reviews.freebsd.org/D26975 --- sys/arm64/arm64/mp_machdep.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/sys/arm64/arm64/mp_machdep.c b/sys/arm64/arm64/mp_machdep.c index 8d5d82879571..3b1a8cc89cab 100644 --- a/sys/arm64/arm64/mp_machdep.c +++ b/sys/arm64/arm64/mp_machdep.c @@ -364,6 +364,8 @@ intr_pic_ipi_setup(u_int ipi, const char *name, intr_ipi_handler_t *hand, ii->ii_send_arg = isrc; strlcpy(ii->ii_name, name, INTR_IPI_NAMELEN); ii->ii_count = intr_ipi_setup_counters(name); + + PIC_ENABLE_INTR(intr_irq_root_dev, isrc); } static void