From owner-svn-src-all@freebsd.org Wed Oct 4 23:35:11 2017 Return-Path: Delivered-To: svn-src-all@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 65444E23A77; Wed, 4 Oct 2017 23:35:11 +0000 (UTC) (envelope-from cem@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 2F58C76A0D; Wed, 4 Oct 2017 23:35:11 +0000 (UTC) (envelope-from cem@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id v94NZAYT011888; Wed, 4 Oct 2017 23:35:10 GMT (envelope-from cem@FreeBSD.org) Received: (from cem@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id v94NZAgt011886; Wed, 4 Oct 2017 23:35:10 GMT (envelope-from cem@FreeBSD.org) Message-Id: <201710042335.v94NZAgt011886@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: cem set sender to cem@FreeBSD.org using -f From: Conrad Meyer Date: Wed, 4 Oct 2017 23:35:10 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r324291 - head/sys/dev/hwpmc X-SVN-Group: head X-SVN-Commit-Author: cem X-SVN-Commit-Paths: head/sys/dev/hwpmc X-SVN-Commit-Revision: 324291 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 04 Oct 2017 23:35:11 -0000 Author: cem Date: Wed Oct 4 23:35:10 2017 New Revision: 324291 URL: https://svnweb.freebsd.org/changeset/base/324291 Log: hwpmc(4): Add support for extended AMD events Sponsored by: Dell EMC Isilon Modified: head/sys/dev/hwpmc/hwpmc_amd.c head/sys/dev/hwpmc/hwpmc_amd.h Modified: head/sys/dev/hwpmc/hwpmc_amd.c ============================================================================== --- head/sys/dev/hwpmc/hwpmc_amd.c Wed Oct 4 23:03:09 2017 (r324290) +++ head/sys/dev/hwpmc/hwpmc_amd.c Wed Oct 4 23:35:10 2017 (r324291) @@ -108,7 +108,7 @@ static struct amd_descr amd_pmcdesc[AMD_NPMCS] = struct amd_event_code_map { enum pmc_event pe_ev; /* enum value */ - uint8_t pe_code; /* encoded event mask */ + uint16_t pe_code; /* encoded event mask */ uint8_t pe_mask; /* bits allowed in unit mask */ }; Modified: head/sys/dev/hwpmc/hwpmc_amd.h ============================================================================== --- head/sys/dev/hwpmc/hwpmc_amd.h Wed Oct 4 23:03:09 2017 (r324290) +++ head/sys/dev/hwpmc/hwpmc_amd.h Wed Oct 4 23:35:10 2017 (r324291) @@ -64,10 +64,10 @@ #define AMD_PMC_UNITMASK_MOESI 0x1F #define AMD_PMC_UNITMASK 0xFF00 -#define AMD_PMC_EVENTMASK 0x00FF +#define AMD_PMC_EVENTMASK 0xF000000FF #define AMD_PMC_TO_UNITMASK(x) (((x) << 8) & AMD_PMC_UNITMASK) -#define AMD_PMC_TO_EVENTMASK(x) ((x) & 0xFF) +#define AMD_PMC_TO_EVENTMASK(x) (((x) & 0xFF) | (((x) & 0xF00) << 24)) #define AMD_VALID_BITS (AMD_PMC_COUNTERMASK | AMD_PMC_INVERT | \ AMD_PMC_ENABLE | AMD_PMC_INT | AMD_PMC_PC | AMD_PMC_EDGE | \ AMD_PMC_OS | AMD_PMC_USR | AMD_PMC_UNITMASK | AMD_PMC_EVENTMASK)