From owner-svn-src-head@FreeBSD.ORG Wed Jul 10 20:28:37 2013 Return-Path: Delivered-To: svn-src-head@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [8.8.178.115]) by hub.freebsd.org (Postfix) with ESMTP id 706F9354; Wed, 10 Jul 2013 20:28:37 +0000 (UTC) (envelope-from marcel@xcllnt.net) Received: from mail.xcllnt.net (mail.xcllnt.net [50.0.150.214]) by mx1.freebsd.org (Postfix) with ESMTP id 4F0821A29; Wed, 10 Jul 2013 20:28:36 +0000 (UTC) Received: from amoroson-sslvpn-nc.jnpr.net (natint3.juniper.net [66.129.224.36]) (authenticated bits=0) by mail.xcllnt.net (8.14.7/8.14.7) with ESMTP id r6AJxk0W053747 (version=TLSv1/SSLv3 cipher=AES128-SHA bits=128 verify=NO); Wed, 10 Jul 2013 12:59:47 -0700 (PDT) (envelope-from marcel@xcllnt.net) Content-Type: text/plain; charset=us-ascii Mime-Version: 1.0 (Mac OS X Mail 6.5 \(1508\)) Subject: Re: svn commit: r253161 - head/sys/dev/uart From: Marcel Moolenaar In-Reply-To: <201307101409.42228.jhb@freebsd.org> Date: Wed, 10 Jul 2013 12:59:40 -0700 Content-Transfer-Encoding: quoted-printable Message-Id: References: <201307101742.r6AHgKOm024113@svn.freebsd.org> <201307101405.44158.jhb@freebsd.org> <201307101409.42228.jhb@freebsd.org> To: John Baldwin X-Mailer: Apple Mail (2.1508) Cc: svn-src-head@freebsd.org, svn-src-all@freebsd.org, Marcel Moolenaar , src-committers@freebsd.org X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 10 Jul 2013 20:28:37 -0000 On Jul 10, 2013, at 11:09 AM, John Baldwin wrote: > On Wednesday, July 10, 2013 2:05:43 pm John Baldwin wrote: >> On Wednesday, July 10, 2013 1:42:20 pm Marcel Moolenaar wrote: >>> Author: marcel >>> Date: Wed Jul 10 17:42:20 2013 >>> New Revision: 253161 >>> URL: http://svnweb.freebsd.org/changeset/base/253161 >>>=20 >>> Log: >>> Protect against broken hardware. In this particular case, protect = against >>> H/W not de-asserting the interrupt at all. On x86, and because of = the >>> following conditions, this results in a hard hang with interrupts = disabled: >>> 1. The uart(4) driver uses a spin lock to protect against = concurrent >>> access to the H/W. Spin locks disable and restore interrupts. >>> 2. Restoring the interrupt on x86 always writes the flags = register. Even >>> if we're restoring the interrupt from disabled to disabled. >>> 3. The x86 CPU has a short window in which interrupts are enabled = when the >>> flags register is written. >>=20 >> Do you have proof of this? No. I only have proof of a hard hang during auto configuration that cannot be fixed in any other way than not to setup the interrupt at all. --=20 Marcel Moolenaar marcel@xcllnt.net