From owner-freebsd-mips@FreeBSD.ORG Mon Aug 27 15:12:19 2012 Return-Path: Delivered-To: freebsd-mips@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [69.147.83.52]) by hub.freebsd.org (Postfix) with ESMTP id EDAAC1065690; Mon, 27 Aug 2012 15:12:18 +0000 (UTC) (envelope-from tim@kientzle.com) Received: from monday.kientzle.com (99-115-135-74.uvs.sntcca.sbcglobal.net [99.115.135.74]) by mx1.freebsd.org (Postfix) with ESMTP id BC06E8FC08; Mon, 27 Aug 2012 15:12:18 +0000 (UTC) Received: (from root@localhost) by monday.kientzle.com (8.14.4/8.14.4) id q7RFC818091514; Mon, 27 Aug 2012 15:12:08 GMT (envelope-from tim@kientzle.com) Received: from [192.168.2.143] (CiscoE3000 [192.168.1.65]) by kientzle.com with SMTP id 8wvqwunvxbytgk5wqkfzrzju8s; Mon, 27 Aug 2012 15:12:08 +0000 (UTC) (envelope-from tim@kientzle.com) Mime-Version: 1.0 (Apple Message framework v1278) Content-Type: text/plain; charset=us-ascii From: Tim Kientzle X-Priority: 3 (Normal) In-Reply-To: Date: Mon, 27 Aug 2012 08:12:07 -0700 Content-Transfer-Encoding: quoted-printable Message-Id: References: <6D83AF9D-577B-4C83-84B7-C4E3B32695FC@bsdimp.com> To: Warner Losh X-Mailer: Apple Mail (2.1278) Cc: Hans Petter Selasky , freebsd-arm@freebsd.org, freebsd-mips@freebsd.org, freebsd-arch@freebsd.org Subject: Re: Partial cacheline flush problems on ARM and MIPS X-BeenThere: freebsd-mips@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Porting FreeBSD to MIPS List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 27 Aug 2012 15:12:19 -0000 On Aug 27, 2012, at 6:38 AM, Warner Losh wrote: >=20 > On Aug 27, 2012, at 12:06 AM, Hans Petter Selasky wrote: >=20 >> Hi, >> Correct. >>=20 >>> We also need some rules about working with buffers obtained from >>> bus_dmamem_alloc() and external buffers passed to bus_dmamap_load(). = I >>> think the rule should be that a buffer obtained from = bus_dmamem_alloc(), >>> or more formally any region of memory mapped by a bus_dmamap_load(), = is >>> a single logical object which can only be accessed by one entity at = a >>> time. That means that there cannot be two concurrent DMA operations >>> happening in different regions of the same buffer, nor can DMA and = CPU >>> access be happening concurrently even if in different parts of the >>> buffer. =20 >>=20 >> Is this something which we can fix using a simple = __align(USB_DMA_ALIGN) on elements in C-structures which are allowed to = be DMA loaded. >=20 > No. I don't think so. the reason is that you can't define = USB_DMA_ALGIN to be a constant on MIPS, at least, or I think ARM because = that's determined at run time. But don't mbuf structures do pretty much what Hans is suggesting? Why is mbuf okay? Tim