From owner-svn-src-head@freebsd.org Fri Nov 17 04:10:54 2017 Return-Path: Delivered-To: svn-src-head@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 4A96FDB989D; Fri, 17 Nov 2017 04:10:54 +0000 (UTC) (envelope-from jhibbits@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 1792678F0F; Fri, 17 Nov 2017 04:10:54 +0000 (UTC) (envelope-from jhibbits@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id vAH4Arur089451; Fri, 17 Nov 2017 04:10:53 GMT (envelope-from jhibbits@FreeBSD.org) Received: (from jhibbits@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id vAH4Arba089450; Fri, 17 Nov 2017 04:10:53 GMT (envelope-from jhibbits@FreeBSD.org) Message-Id: <201711170410.vAH4Arba089450@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: jhibbits set sender to jhibbits@FreeBSD.org using -f From: Justin Hibbits Date: Fri, 17 Nov 2017 04:10:53 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r325926 - head/sys/powerpc/ofw X-SVN-Group: head X-SVN-Commit-Author: jhibbits X-SVN-Commit-Paths: head/sys/powerpc/ofw X-SVN-Commit-Revision: 325926 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.25 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 17 Nov 2017 04:10:54 -0000 Author: jhibbits Date: Fri Nov 17 04:10:52 2017 New Revision: 325926 URL: https://svnweb.freebsd.org/changeset/base/325926 Log: Stop special casing 32-bit AIM in memory parsing There's no need to special case 32-bit AIM to short circuit processing. Some AIM CPUs can handle 36 bit addresses, and 64-bit CPUs can run 32-bit OSes, so this will allow us to expand for that in the future if we desire. Modified: head/sys/powerpc/ofw/ofw_machdep.c Modified: head/sys/powerpc/ofw/ofw_machdep.c ============================================================================== --- head/sys/powerpc/ofw/ofw_machdep.c Fri Nov 17 02:59:28 2017 (r325925) +++ head/sys/powerpc/ofw/ofw_machdep.c Fri Nov 17 04:10:52 2017 (r325926) @@ -184,14 +184,6 @@ parse_ofw_memory(phandle_t node, const char *prop, str i = 0; j = 0; while (i < sz/sizeof(cell_t)) { - #if !defined(__powerpc64__) && !defined(BOOKE) - /* On 32-bit PPC (OEA), ignore regions starting above 4 GB */ - if (address_cells > 1 && OFmem[i] > 0) { - i += address_cells + size_cells; - continue; - } - #endif - output[j].mr_start = OFmem[i++]; if (address_cells == 2) { output[j].mr_start <<= 32; @@ -204,19 +196,20 @@ parse_ofw_memory(phandle_t node, const char *prop, str output[j].mr_size += OFmem[i++]; } - #if !defined(__powerpc64__) && !defined(BOOKE) - /* Book-E can support 36-bit addresses. */ + if (output[j].mr_start > BUS_SPACE_MAXADDR) + continue; + /* - * Check for memory regions extending above 32-bit - * memory space, and restrict them to stay there. + * Constrain memory to that which we can access. + * 32-bit AIM can only reference 32 bits of address currently, + * but Book-E can access 36 bits. */ if (((uint64_t)output[j].mr_start + - (uint64_t)output[j].mr_size) > - BUS_SPACE_MAXADDR_32BIT) { - output[j].mr_size = BUS_SPACE_MAXADDR_32BIT - - output[j].mr_start; + (uint64_t)output[j].mr_size - 1) > + BUS_SPACE_MAXADDR) { + output[j].mr_size = BUS_SPACE_MAXADDR - + output[j].mr_start + 1; } - #endif j++; }