From owner-freebsd-ppc@FreeBSD.ORG Sun Sep 28 15:14:46 2008 Return-Path: Delivered-To: freebsd-ppc@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 6FB6A1065686 for ; Sun, 28 Sep 2008 15:14:46 +0000 (UTC) (envelope-from nwhitehorn@freebsd.org) Received: from adsum.doit.wisc.edu (adsum.doit.wisc.edu [144.92.197.210]) by mx1.freebsd.org (Postfix) with ESMTP id 431988FC1A for ; Sun, 28 Sep 2008 15:14:46 +0000 (UTC) (envelope-from nwhitehorn@freebsd.org) MIME-version: 1.0 Content-transfer-encoding: 7BIT Content-type: text/plain; charset=ISO-8859-1; format=flowed Received: from avs-daemon.smtpauth1.wiscmail.wisc.edu by smtpauth1.wiscmail.wisc.edu (Sun Java(tm) System Messaging Server 6.3-6.03 (built Mar 14 2008; 32bit)) id <0K7W00400VOL2S00@smtpauth1.wiscmail.wisc.edu> for freebsd-ppc@freebsd.org; Sun, 28 Sep 2008 10:14:45 -0500 (CDT) Received: from trantor.tachypleus.net (adsl-76-204-100-161.dsl.mdsnwi.sbcglobal.net [76.204.100.161]) by smtpauth1.wiscmail.wisc.edu (Sun Java(tm) System Messaging Server 6.3-6.03 (built Mar 14 2008; 32bit)) with ESMTPSA id <0K7W00KQTVOKYI20@smtpauth1.wiscmail.wisc.edu> for freebsd-ppc@freebsd.org; Sun, 28 Sep 2008 10:14:45 -0500 (CDT) Date: Sun, 28 Sep 2008 10:19:11 -0500 From: Nathan Whitehorn In-reply-to: To: Marco Trillo Message-id: <48DFA06F.20607@freebsd.org> X-Spam-Report: AuthenticatedSender=yes, SenderIP=76.204.100.161 X-Spam-PmxInfo: Server=avs-11, Version=5.4.1.325704, Antispam-Engine: 2.6.0.325393, Antispam-Data: 2008.9.28.145525, SenderIP=76.204.100.161 References: User-Agent: Thunderbird 2.0.0.16 (X11/20080814) Cc: freebsd-ppc@freebsd.org Subject: Re: Fatal kernel trap on 7400 G4 processors X-BeenThere: freebsd-ppc@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Porting FreeBSD to the PowerPC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 28 Sep 2008 15:14:46 -0000 Marco Trillo wrote: > Hi all, > > Recent 8.0-current kernels cause a "fatal kernel trap" on 7400 G4 processors: > > fatal kernel trap > > exception = 0x7 (program) > srr0 = 0x5336bc > srr1 = 0x83032 > lr = 0x5334b4 > > Stopped at 0x5336bc mfspr 0, dccr > > The address 0x5336bc corresponds to function cpu_setup() in powerpc/cpu.c: > > 5336b4: 7f 9e 00 00 cmpw cr7,r30,r0 > 5336b8: 40 be 02 94 bne+ cr7,53394c > 5336bc: 7c 1a fa a6 mfdccr r0 <<<<< here > 5336c0: 3d 20 00 5f lis r9,95 > > I tracked the line to the following code in cpu.c: > > l3cr_config = mfspr(SPR_L3CR); <<<< here > > /* Fallthrough */ > > In include/spr.h I see the following: > > #define SPR_L3CR 0x3fa /* .6. L3 Control Register */ > #define SPR_DCCR 0x3fa /* 4.. Data Cache Cachability Register */ > > So it seems that the 7400 processor doesn't have these registers so it > causes a fault. Apparently only the MPC745x CPUs have an L3 cache, and I just updated cpu.c to reflect that. For G5 support, I wrote a piece of code that you can put in EXEC_PGM that writes a value to SPRG2 if a trap was taken, then tries to execute a 64-bit instruction to see if the CPU is 64-bit. I think we should do something similar to detect cache presence, Altivec support and such things. Since we can do this when the system is further into booting, we should be able to use the regular trap handlers. Is there a way to catch traps instead of panicing? -Nathan