From owner-svn-src-user@FreeBSD.ORG Tue May 10 01:31:42 2011 Return-Path: Delivered-To: svn-src-user@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 2A46C106564A; Tue, 10 May 2011 01:31:42 +0000 (UTC) (envelope-from marcel@xcllnt.net) Received: from mail.xcllnt.net (mail.xcllnt.net [70.36.220.4]) by mx1.freebsd.org (Postfix) with ESMTP id F06738FC0C; Tue, 10 May 2011 01:31:41 +0000 (UTC) Received: from dhcp-192-168-2-44.wifi.xcllnt.net (atm.xcllnt.net [70.36.220.6]) (authenticated bits=0) by mail.xcllnt.net (8.14.4/8.14.4) with ESMTP id p4A1LALE055420 (version=TLSv1/SSLv3 cipher=AES128-SHA bits=128 verify=NO); Mon, 9 May 2011 18:21:14 -0700 (PDT) (envelope-from marcel@xcllnt.net) Mime-Version: 1.0 (Apple Message framework v1084) Content-Type: text/plain; charset=us-ascii From: Marcel Moolenaar In-Reply-To: <201105090705.p49756Ff080416@svn.freebsd.org> Date: Mon, 9 May 2011 18:21:09 -0700 Content-Transfer-Encoding: 7bit Message-Id: References: <201105090705.p49756Ff080416@svn.freebsd.org> To: Andriy Gapon X-Mailer: Apple Mail (2.1084) Cc: src-committers@freebsd.org, svn-src-user@freebsd.org Subject: Re: svn commit: r221677 - in user/avg/xcpu/sys: amd64/amd64 kern sys X-BeenThere: svn-src-user@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: "SVN commit messages for the experimental " user" src tree" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 10 May 2011 01:31:42 -0000 On May 9, 2011, at 12:05 AM, Andriy Gapon wrote: > Author: avg > Date: Mon May 9 07:05:06 2011 > New Revision: 221677 > URL: http://svn.freebsd.org/changeset/base/221677 > > Log: > re-implement hard stopping of CPUs and use it enforce panic(9) context While you're here... I'd like to change the whole logic and turn it into a rendezvous. One CPU, the one panicing can proceed. But I'd like to add the ability from the debugger to switch onto a different CPU. Such makes it possible to implement commands that show control and status registers, perform function calls on specific CPUs, as well as dump on-chip TLB entries and cache line contents if the CPU/platform supports it. Thoughts? -- Marcel Moolenaar marcel@xcllnt.net