From nobody Wed Aug 31 11:15:36 2022 X-Original-To: dev-commits-src-all@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 4MHhRy5rCyz4b43k for ; Wed, 31 Aug 2022 11:15:42 +0000 (UTC) (envelope-from tsoome@me.com) Received: from ci74p00im-qukt09081701.me.com (ci74p00im-qukt09081701.me.com [17.57.156.6]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 4MHhRy5FK3z4FrN for ; Wed, 31 Aug 2022 11:15:42 +0000 (UTC) (envelope-from tsoome@me.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=me.com; s=1a1hai; t=1661944541; bh=HVJs25VGiXwCVGyjt9WGdpU0AAaWtDysR3+L6jEmdQk=; h=From:Message-Id:Content-Type:Mime-Version:Subject:Date:To; b=cYpRPugy5Lzu5C/+pEXDIl9K7TffwrNtcrEL9B3eASsz7iKL/FE5N5fBQ+mFzfdDm jsrfSes2uJh+i0v4DUFaj3eKnHkiuhyco/KjfdZmMusWzc/HzqNOnr/9zk8xOnlYpV ipHIklqe/rIvRs7a9l1hNU7DXiNd47lMahhWEaFsSgb90vPgWrIjVdc3QxpWgChNqF Dil2yiNb6gRHLauvvyzDFRPOZVhZWHKA12Sf00ob5aRK75rKkTps/ScFRhDwWUtA+P aCIu5RVxmDpahJnW9ensA8PEhORP9KjsgGxLO4jQRB61IxavcmizI1Vq49b/l9Rl1Q 20oCplKc4h7Ow== Received: from smtpclient.apple (ci77p00im-dlb-asmtp-mailmevip.me.com [17.57.156.26]) by ci74p00im-qukt09081701.me.com (Postfix) with ESMTPSA id 85FB046C07CD; Wed, 31 Aug 2022 11:15:39 +0000 (UTC) From: Toomas Soome Message-Id: <0DCA177E-9FD9-4DF8-A7EB-C29CA44B5116@me.com> Content-Type: multipart/alternative; boundary="Apple-Mail=_0C935628-E893-401A-9B4F-97ADC5A55F9E" List-Id: Commit messages for all branches of the src repository List-Archive: https://lists.freebsd.org/archives/dev-commits-src-all List-Help: List-Post: List-Subscribe: List-Unsubscribe: Sender: owner-dev-commits-src-all@freebsd.org X-BeenThere: dev-commits-src-all@freebsd.org Mime-Version: 1.0 (Mac OS X Mail 16.0 \(3696.120.41.1.1\)) Subject: Re: git: e3572eb65473 - main - Allocate event for DMC-620 and CMN-600 controllers PMU. Add events supported by DMC-620 and CMN-600 controllers PMU. Date: Wed, 31 Aug 2022 14:15:36 +0300 In-Reply-To: <0F57FEEE-BDC0-4CE1-9349-D7E12556E158@freebsd.org> Cc: "Bjoern A. Zeeb" , Toomas Soome , "src-committers@freebsd.org" , "dev-commits-src-all@freebsd.org" , "dev-commits-src-main@freebsd.org" To: Jessica Clarke References: <202206262217.25QMHOuH076130@gitrepo.freebsd.org> <1E37449E-B6C8-47A5-AD79-34F24138CC64@freebsd.org> <0F57FEEE-BDC0-4CE1-9349-D7E12556E158@freebsd.org> X-Mailer: Apple Mail (2.3696.120.41.1.1) X-Proofpoint-GUID: gnwui5KK5E_qIa3oBjQIwtUdNbvhGVKQ X-Proofpoint-ORIG-GUID: gnwui5KK5E_qIa3oBjQIwtUdNbvhGVKQ X-Proofpoint-Virus-Version: =?UTF-8?Q?vendor=3Dfsecure_engine=3D1.1.170-22c6f66c430a71ce266a39bfe25bc?= =?UTF-8?Q?2903e8d5c8f:6.0.138,18.0.790,17.11.62.513.0000000_definitions?= =?UTF-8?Q?=3D2022-01-12=5F03:2020-02-14=5F02,2022-01-12=5F03,2021-12-02?= =?UTF-8?Q?=5F01_signatures=3D0?= X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 malwarescore=0 bulkscore=0 mlxlogscore=999 phishscore=0 suspectscore=0 adultscore=0 spamscore=0 mlxscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2206140000 definitions=main-2208310056 X-Spamd-Bar: ---- Authentication-Results: mx1.freebsd.org; none X-Rspamd-Queue-Id: 4MHhRy5FK3z4FrN X-Rspamd-Pre-Result: action=no action; module=replies; Message is reply to one we originated X-Spamd-Result: default: False [-4.00 / 15.00]; REPLY(-4.00)[] X-ThisMailContainsUnwantedMimeParts: N --Apple-Mail=_0C935628-E893-401A-9B4F-97ADC5A55F9E Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=utf-8 Please see https://reviews.freebsd.org/D36401 = thanks, toomas > On 31. Aug 2022, at 01:05, Jessica Clarke wrote: >=20 > On 30 Aug 2022, at 22:51, Bjoern A. Zeeb > wrote: >>=20 >> On Tue, 30 Aug 2022, Jessica Clarke wrote: >>=20 >> Hi Jessica, >>=20 >>> On 27 Jun 2022, at 01:58, Bjoern A. Zeeb wrote: >>>>=20 >>>> On Mon, 27 Jun 2022, Jessica Clarke wrote: >>>>=20 >>>> Hi, >>>>=20 >>>>> On 27 Jun 2022, at 01:26, Bjoern A. Zeeb wrote: >>>>>>=20 >>>>>> On Mon, 27 Jun 2022, Jessica Clarke wrote: >>>>>>=20 >>>>>>> On 26 Jun 2022, at 23:17, Toomas Soome = wrote: >>>>>>>>=20 >>>>>>>> The branch main has been updated by tsoome: >>>>>>>>=20 >>>>>>>> URL: = https://cgit.FreeBSD.org/src/commit/?id=3De3572eb654733a94e1e765fe9e95e057= 9981d851 >>>>>>>>=20 >>>>>>>> commit e3572eb654733a94e1e765fe9e95e0579981d851 >>>>>>>> Author: Aleksandr Rybalko >>>>>>>> AuthorDate: 2022-02-16 00:19:19 +0000 >>>>>>>> Commit: Toomas Soome >>>>>>>> CommitDate: 2022-06-26 18:52:26 +0000 >>>>>>>>=20 >>>>>>>> Allocate event for DMC-620 and CMN-600 controllers PMU. Add = events supported by DMC-620 and CMN-600 controllers PMU. >>>>>>>>=20 >>>>>>>> Allocate event for DMC-620 and CMN-600 controllers PMU. >>>>>>>> Add events supported by DMC-620 and CMN-600 controllers PMU. >>>>>>>>=20 >>>>>>>> Reviewed by: bz >>>>>>>> Sponsored By: ARM >>>>>>>> Sponsored By: Ampere Computing >>>>>>>> Differential Revision: https://reviews.freebsd.org/D35609 >>>>>>>=20 >>>>>>> This includes the following (skipped due to lines) diff: >>>>>>>=20 >>>>>>>> * 0x14100 0x0100 ARMv8 events >>>>>>>> + * 0x14200 0x0020 ARM DMC-620 clkdiv2 events >>>>>>>> + * 0x14220 0x0080 ARM DMC-620 clk events >>>>>>>> + * 0x14300 0x0100 ARM CMN-600 events >>>>>>>=20 >>>>>>>=20 >>>>>>> Not enough space was allocated for Armv8 events as it goes up to = 0x3ff >>>>>>> in Armv8 (and beyond in later versions of the architecture). = Downstream >>>>>>> we extend this range in CheriBSD as required for Morello=E2=80=99s= events. >>>>>>> Please relocate these new events well past the end of the = existing >>>>>>> Armv8 events so the space can remain contiguous. >>>>>>=20 >>>>>> Should this be 0x3ff then as well btw? >>>>>> = https://github.com/CTSRD-CHERI/cheribsd/commit/4ea869cd8b717ca0b07672eb7ac= c99bf949249de >>>>>=20 >>>>> Well, 0x400 for count not max, but yes. We only extended as far as = we >>>>> needed, not to cover the entire range (but intended to eventually >>>>> upstream it as the full v8 range). >>>>>=20 >>>>>> Looking more closely it seems from ARMv8.1 onwards it goes up to = 0xFFFF >>>>>> if I read 'Table D8-7 Allocation of the PMU event number space' = of ARM >>>>>> DDI 0487H.a correctly? >>>>>=20 >>>>> Yes, if you want to cover all the v8.1 space then you need to go = that >>>>> high too, but it=E2=80=99ll get quite sparse in that range so = it=E2=80=99s unclear if >>>>> we want to go ahead and do that already or try and be smarter (the >>>>> current EVENT_xH list would get a bit silly). We should probably >>>>> reserve all of it though at least so we can if we want to in = future. >>>>=20 >>>> I'll let you and Toomas sort that out. I am just trying to fix the >>>> build breakage as I kind-of pushed him to get the remaining bits in >>>> by accepting that review after scrolling through and it looking >>>> reasonable and addressing all comments from the previous review. >>>> That was all to unbreak an already earlier build breakage. >>>>=20 >>>> Given it wasn't too late for me I was trying to get through it >>>> before falling asleep soon as well, especially now that the >>>> thunderstorms seems to have mostly passed. >>>=20 >>> Nobody ever got round to addressing this, and it is in fact causing = us >>> issues downstream now. However, there=E2=80=99s a rather more = glaring problem: >>>=20 >>>> @@ -1313,6 +1475,10 @@ pmc_init(void) >>>>=20 >>>> /* Fill soft events information. */ >>>> pmc_class_table[n++] =3D &soft_class_table_descr; >>>> + >>>> + pmc_class_table[n++] =3D &cmn600_pmu_class_table_descr; >>>> + pmc_class_table[n++] =3D &dmc620_pmu_cd2_class_table_descr; >>>> + pmc_class_table[n++] =3D &dmc620_pmu_c_class_table_descr; >>>=20 >>> This doesn=E2=80=99t work (even if you ifdef it appropriately like = now exists >>> upstream). If there is no CMN-600 etc then PMC_CLASS_TABLE_SIZE, = i.e. >>> cpu_info.pm_nclass, is not going to include those, so you cannot add >>> them to pmc_class_table otherwise you have a buffer overflow. >>=20 >> I am just replying really given I am on Cc: hoping that Toomas will = get to this. >>=20 >> pmc_init() is libpmc, right? Does a simple #if 0 around these avert = all >> issues for now or do the kernel bits also need backing out? >>=20 >> I only have vague memories of multiple commit to unbreak this one = from >> that night (which tried to fix a previous different breakage). >> Backing out everything might be more tedious than just reverting the >> commit hence asking if "disabling" it does fix the problems. >=20 > The only commit to libpmc.c since then was to add the #ifdef. I = believe > the kernel bits can stay, though the event numbers still collide with > what should have been reserved for Armv8-A=E2=80=99s full range, and = what we > reserve downstream as we have hardware that uses those events for > documented counters. >=20 >>> Given >>> this has broken libpmc on large swathes of AArch64 hardware (maybe >>=20 >> That has taken a lot of time for anyone to notice :( >=20 > It also took a long time for anyone to notice how broken libpmcstat = is, > and only a handful of people have noticed it=E2=80=99s totally broken = for PIEs. > People just aren=E2=80=99t using pmc much, especially on !x86=E2=80=A6 >=20 > Jess >=20 >>> without CHERI the memory corruption happens to not trample over >>> anything important for now, but who knows), can we please revert = this >>> patch until a fixed version exists, with both the event numbers >>> reallocated and libpmc made suitably dynamic so as to not introduce >>> buffer overflows? >>>=20 >>> Note that cmn600 only has an ACPI attachment so FDT-based systems = will >>> definitely hit this case. >>>=20 >>> Jess >>>=20 >>>=20 >>=20 >> --=20 >> Bjoern A. Zeeb r15:7 --Apple-Mail=_0C935628-E893-401A-9B4F-97ADC5A55F9E Content-Transfer-Encoding: quoted-printable Content-Type: text/html; charset=utf-8 Please see https://reviews.freebsd.org/D36401

thanks,
toomas

On 31. Aug 2022, at 01:05, Jessica Clarke = <jrtc27@freebsd.org> wrote:

On 30 Aug 2022, at 22:51, Bjoern A. Zeeb <bz@FreeBSD.org> = wrote:

On Tue, 30 Aug 2022, Jessica Clarke wrote:

Hi Jessica,

On 27 Jun 2022, at 01:58, Bjoern A. Zeeb <bz@FreeBSD.org> = wrote:

On Mon, 27 Jun 2022, Jessica Clarke wrote:

Hi,

On 27 Jun 2022, at 01:26, Bjoern A. Zeeb <bz@FreeBSD.org> = wrote:

On Mon, 27 Jun 2022, Jessica Clarke wrote:

On 26 Jun 2022, at = 23:17, Toomas Soome <tsoome@FreeBSD.org> wrote:

The branch main has been updated = by tsoome:

URL: https://cgit.FreeBSD.org/src/commit/?id=3De3572eb654733a94e1e76= 5fe9e95e0579981d851

commit = e3572eb654733a94e1e765fe9e95e0579981d851
Author: Aleksandr = Rybalko <ray@freebsd.org>
AuthorDate: 2022-02-16 = 00:19:19 +0000
Commit: Toomas Soome <tsoome@FreeBSD.org>
CommitDate: = 2022-06-26 18:52:26 +0000

Allocate event = for DMC-620 and CMN-600 controllers PMU. Add events supported by DMC-620 = and CMN-600 controllers PMU.

Allocate event = for DMC-620 and CMN-600 controllers PMU.
Add events = supported by DMC-620 and CMN-600 controllers PMU.

Reviewed by: bz
Sponsored By: ARM
Sponsored By: Ampere Computing
Differential = Revision: https://reviews.freebsd.org/D35609

This includes the following = (skipped due to lines) diff:

* 0x14100 0x0100 ARMv8 = events
+ * 0x14200 0x0020 ARM = DMC-620 clkdiv2 events
+ * 0x14220 = 0x0080 = = ARM DMC-620 clk events
+ * 0x14300 = 0x0100 = = ARM CMN-600 events


Not enough space was allocated for Armv8 events as it goes up = to 0x3ff
in Armv8 (and beyond in later versions of the = architecture). Downstream
we extend this range in CheriBSD = as required for Morello=E2=80=99s events.
Please relocate = these new events well past the end of the existing
Armv8 = events so the space can remain contiguous.

Should this be 0x3ff then as well btw?
https://github.com/CTSRD-CHERI/cheribsd/commit/4ea869cd8b717ca0= b07672eb7acc99bf949249de

Well, 0x400 for count not max, but yes. We only extended as = far as we
needed, not to cover the entire range (but = intended to eventually
upstream it as the full v8 = range).

Looking more closely it seems from ARMv8.1 onwards it goes up = to 0xFFFF
if I read 'Table D8-7 Allocation of the PMU = event number space' of ARM
DDI 0487H.a correctly?

Yes, if you want to cover all the = v8.1 space then you need to go that
high too, but it=E2=80=99= ll get quite sparse in that range so it=E2=80=99s unclear if
we want to go ahead and do that already or try and be smarter = (the
current EVENT_xH list would get a bit silly). We = should probably
reserve all of it though at least so we = can if we want to in future.

I'll let you and Toomas sort that out. I am just trying to = fix the
build breakage as I kind-of pushed him to get the = remaining bits in
by accepting that review after scrolling = through and it looking
reasonable and addressing all = comments from the previous review.
That was all to unbreak = an already earlier build breakage.

Given it = wasn't too late for me I was trying to get through it
before= falling asleep soon as well, especially now that the
thunderstorms seems to have mostly passed.

Nobody ever got round to = addressing this, and it is in fact causing us
issues = downstream now. However, there=E2=80=99s a rather more glaring = problem:

@@ -1313,6 +1475,10 @@ pmc_init(void)

= /* Fill soft events information. */
= pmc_class_table[n++] =3D &soft_class_table_descr;
+
+ pmc_class_table[n++] =3D = &cmn600_pmu_class_table_descr;
+ = pmc_class_table[n++] =3D = &dmc620_pmu_cd2_class_table_descr;
+ = pmc_class_table[n++] =3D &dmc620_pmu_c_class_table_descr;

This doesn=E2=80=99t work (even = if you ifdef it appropriately like now exists
upstream). = If there is no CMN-600 etc then PMC_CLASS_TABLE_SIZE, i.e.
cpu_info.pm_nclass, is not going to include those, so you = cannot add
them to pmc_class_table otherwise you have a = buffer overflow.

I am just = replying really given I am on Cc: hoping that Toomas will get to = this.

pmc_init() is libpmc, right? Does a = simple #if 0 around these avert all
issues for now or do = the kernel bits also need backing out?

I = only have vague memories of multiple commit to unbreak this one from
that night (which tried to fix a previous different = breakage).
Backing out everything might be more tedious = than just reverting the
commit hence asking if "disabling" = it does fix the problems.

The only = commit to libpmc.c since then was to add the #ifdef. I believe
the kernel = bits can stay, though the event numbers still collide with
what should = have been reserved for Armv8-A=E2=80=99s full range, and what = we
reserve = downstream as we have hardware that uses those events for
documented = counters.

Given
this = has broken libpmc on large swathes of AArch64 hardware (maybe

That has taken a lot of time for = anyone to notice :(

It also took a long time for anyone to notice how broken = libpmcstat is,
and only a handful of people have noticed it=E2=80=99s = totally broken for PIEs.
People just aren=E2=80=99t using pmc much, especially on = !x86=E2=80=A6

Jess

without CHERI the memory = corruption happens to not trample over
anything important = for now, but who knows), can we please revert this
patch = until a fixed version exists, with both the event numbers
reallocated and libpmc made suitably dynamic so as to not = introduce
buffer overflows?

Note that cmn600 only has an ACPI attachment so FDT-based = systems will
definitely hit this case.

Jess



-- 
Bjoern A. = Zeeb r15:7

= --Apple-Mail=_0C935628-E893-401A-9B4F-97ADC5A55F9E--