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Date:      Wed, 18 Sep 2019 06:50:29 +0000 (UTC)
From:      "Jayachandran C." <jchandra@FreeBSD.org>
To:        src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-12@freebsd.org
Subject:   svn commit: r352468 - stable/12/sys/dev/pci
Message-ID:  <201909180650.x8I6oTit082365@repo.freebsd.org>

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Author: jchandra
Date: Wed Sep 18 06:50:29 2019
New Revision: 352468
URL: https://svnweb.freebsd.org/changeset/base/352468

Log:
  MFC r340595-r340597
  
  r340595:
  pci_host_generic: remove unneeded ThunderX2 quirk
  
  The current quirk implementation writes a fixed address to the PCI BAR
  to fix a firmware bug. The PCI BARs are allocated by firmware and will
  change depending on PCI devices present. So using a fixed address here
  is not correct.
  
  This quirk worked around a firmware bug that programmed the MSI-X bar
  of the SATA controller incorrectly. The newer firmware does not have
  this issue, so it is better to drop this quirk altogether.
  
  Reviewed by:	andrew
  Differential Revision:	https://reviews.freebsd.org/D17655
  
  r340596:
  pci_host_generic: allocate resources against devices
  
  Fix up pci_host_generic.c and pci_host_generic_fdt.c to allocate
  resources against devices that requested them. Currently the
  allocation happens against the pcib, which is incorrect.
  
  This is needed for the upcoming changes for fixing up
  pci_host_generic_acpi.c
  
  Reviewed by:	andrew
  Differential Revision:	https://reviews.freebsd.org/D17656
  
  r340597:
  pci_host_generic*: basic implementation of bus range
  
  Both ACPI and FDT support bus ranges for pci host bridges. Update
  pci_host_generic*.[ch] with a default implementation to support this.
  This will be used in the next set of changes for ACPI based host
  bridge. No functional changes in this commit.
  
  Reviewed by:	andrew
  Differential Revision:	https://reviews.freebsd.org/D17657

Modified:
  stable/12/sys/dev/pci/pci_host_generic.c
  stable/12/sys/dev/pci/pci_host_generic.h
  stable/12/sys/dev/pci/pci_host_generic_acpi.c
  stable/12/sys/dev/pci/pci_host_generic_fdt.c
Directory Properties:
  stable/12/   (props changed)

Modified: stable/12/sys/dev/pci/pci_host_generic.c
==============================================================================
--- stable/12/sys/dev/pci/pci_host_generic.c	Wed Sep 18 02:04:41 2019	(r352467)
+++ stable/12/sys/dev/pci/pci_host_generic.c	Wed Sep 18 06:50:29 2019	(r352468)
@@ -69,25 +69,6 @@ __FBSDID("$FreeBSD$");
 	(((func) & PCIE_FUNC_MASK) << PCIE_FUNC_SHIFT)	|	\
 	((reg) & PCIE_REG_MASK))
 
-typedef void (*pci_host_generic_quirk_function)(device_t);
-
-struct pci_host_generic_quirk_entry {
-	int impl;
-	int part;
-	int var;
-	int rev;
-	pci_host_generic_quirk_function func;
-};
-
-struct pci_host_generic_block_entry {
-	int impl;
-	int part;
-	int var;
-	int rev;
-	int bus;
-	int slot;
-};
-
 /* Forward prototypes */
 
 static uint32_t generic_pcie_read_config(device_t dev, u_int bus, u_int slot,
@@ -100,24 +81,6 @@ static int generic_pcie_read_ivar(device_t dev, device
 static int generic_pcie_write_ivar(device_t dev, device_t child, int index,
     uintptr_t value);
 
-#if defined(__aarch64__)
-static void pci_host_generic_apply_quirks(device_t);
-static void thunderx2_ahci_bar_quirk(device_t);
-
-struct pci_host_generic_quirk_entry pci_host_generic_quirks[] =
-{
-	{CPU_IMPL_CAVIUM, CPU_PART_THUNDERX2, 0, 0, thunderx2_ahci_bar_quirk},
-	{0, 0, 0, 0, NULL}
-};
-
-struct pci_host_generic_block_entry pci_host_generic_blocked[] =
-{
-	/* ThunderX2 AHCI on second socket */
-	{CPU_IMPL_CAVIUM, CPU_PART_THUNDERX2, 0, 0, 0x80, 0x10},
-	{0, 0, 0, 0, 0, 0}
-};
-#endif
-
 int
 pci_host_generic_core_attach(device_t dev)
 {
@@ -171,34 +134,9 @@ pci_host_generic_core_attach(device_t dev)
 		return (error);
 	}
 
-#if defined(__aarch64__)
-	pci_host_generic_apply_quirks(dev);
-#endif
-
 	return (0);
 }
 
-#if defined(__aarch64__)
-static void
-pci_host_generic_apply_quirks(device_t dev)
-{
-	struct pci_host_generic_quirk_entry *quirk;
-
-	quirk = pci_host_generic_quirks;
-	while (1) {
-		if (quirk->impl == 0)
-			break;
-
-		if (CPU_MATCH(CPU_IMPL_MASK | CPU_PART_MASK,
-		    quirk->impl, quirk->part, quirk->var, quirk->rev) &&
-		    quirk->func != NULL)
-			quirk->func(dev);
-
-		quirk++;
-	}
-}
-#endif
-
 static uint32_t
 generic_pcie_read_config(device_t dev, u_int bus, u_int slot,
     u_int func, u_int reg, int bytes)
@@ -208,32 +146,15 @@ generic_pcie_read_config(device_t dev, u_int bus, u_in
 	bus_space_tag_t	t;
 	uint64_t offset;
 	uint32_t data;
-#if defined(__aarch64__)
-	struct pci_host_generic_block_entry *block;
-#endif
 
-	if ((bus > PCI_BUSMAX) || (slot > PCI_SLOTMAX) ||
-	    (func > PCI_FUNCMAX) || (reg > PCIE_REGMAX))
+	sc = device_get_softc(dev);
+	if ((bus < sc->bus_start) || (bus > sc->bus_end))
 		return (~0U);
+	if ((slot > PCI_SLOTMAX) || (func > PCI_FUNCMAX) ||
+	    (reg > PCIE_REGMAX))
+		return (~0U);
 
-#if defined(__aarch64__)
-	block = pci_host_generic_blocked;
-	while (1) {
-		if (block->impl == 0)
-			break;
-
-		if (CPU_MATCH(CPU_IMPL_MASK | CPU_PART_MASK,
-		    block->impl, block->part, block->var, block->rev) &&
-		    block->bus == bus && block->slot == slot)
-			return (~0);
-
-		block++;
-	}
-#endif
-
-	sc = device_get_softc(dev);
-
-	offset = PCIE_ADDR_OFFSET(bus, slot, func, reg);
+	offset = PCIE_ADDR_OFFSET(bus - sc->bus_start, slot, func, reg);
 	t = sc->bst;
 	h = sc->bsh;
 
@@ -263,14 +184,15 @@ generic_pcie_write_config(device_t dev, u_int bus, u_i
 	bus_space_tag_t t;
 	uint64_t offset;
 
-	if ((bus > PCI_BUSMAX) || (slot > PCI_SLOTMAX) ||
-	    (func > PCI_FUNCMAX) || (reg > PCIE_REGMAX))
+	sc = device_get_softc(dev);
+	if ((bus < sc->bus_start) || (bus > sc->bus_end))
 		return;
+	if ((slot > PCI_SLOTMAX) || (func > PCI_FUNCMAX) ||
+	    (reg > PCIE_REGMAX))
+		return;
 
-	sc = device_get_softc(dev);
+	offset = PCIE_ADDR_OFFSET(bus - sc->bus_start, slot, func, reg);
 
-	offset = PCIE_ADDR_OFFSET(bus, slot, func, reg);
-
 	t = sc->bst;
 	h = sc->bsh;
 
@@ -301,14 +223,11 @@ generic_pcie_read_ivar(device_t dev, device_t child, i
     uintptr_t *result)
 {
 	struct generic_pcie_core_softc *sc;
-	int secondary_bus;
 
 	sc = device_get_softc(dev);
 
 	if (index == PCIB_IVAR_BUS) {
-		/* this pcib adds only pci bus 0 as child */
-		secondary_bus = 0;
-		*result = secondary_bus;
+		*result = sc->bus_start;
 		return (0);
 
 	}
@@ -390,7 +309,7 @@ pci_host_generic_core_alloc_resource(device_t dev, dev
 
 	rm = generic_pcie_rman(sc, type);
 	if (rm == NULL)
-		return (BUS_ALLOC_RESOURCE(device_get_parent(dev), dev,
+		return (BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
 		    type, rid, start, end, count, flags));
 
 	if (bootverbose) {
@@ -472,22 +391,3 @@ static device_method_t generic_pcie_methods[] = {
 
 DEFINE_CLASS_0(pcib, generic_pcie_core_driver,
     generic_pcie_methods, sizeof(struct generic_pcie_core_softc));
-
-#if defined(__aarch64__)
-static void thunderx2_ahci_bar_quirk(device_t dev)
-{
-
-	/*
-	 * XXX:
-	 * On ThunderX2, AHCI BAR2 address is wrong. It needs to precisely
-	 * match the one described in datasheet. Fixup it unconditionally.
-	 */
-	if (device_get_unit(dev) == 0) {
-		device_printf(dev, "running AHCI BAR fixup\n");
-		PCIB_WRITE_CONFIG(dev, 0, 16, 0, 0x18, 0x01440000, 4);
-		PCIB_WRITE_CONFIG(dev, 0, 16, 0, 0x1c, 0x40, 4);
-		PCIB_WRITE_CONFIG(dev, 0, 16, 1, 0x18, 0x01450000, 4);
-		PCIB_WRITE_CONFIG(dev, 0, 16, 1, 0x1c, 0x40, 4);
-	}
-}
-#endif

Modified: stable/12/sys/dev/pci/pci_host_generic.h
==============================================================================
--- stable/12/sys/dev/pci/pci_host_generic.h	Wed Sep 18 02:04:41 2019	(r352467)
+++ stable/12/sys/dev/pci/pci_host_generic.h	Wed Sep 18 06:50:29 2019	(r352468)
@@ -56,6 +56,8 @@ struct generic_pcie_core_softc {
 	struct rman		io_rman;
 	struct resource		*res;
 	struct resource		*res1;
+	int			bus_start;
+	int			bus_end;
 	int			ecam;
 	bus_space_tag_t		bst;
 	bus_space_handle_t	bsh;

Modified: stable/12/sys/dev/pci/pci_host_generic_acpi.c
==============================================================================
--- stable/12/sys/dev/pci/pci_host_generic_acpi.c	Wed Sep 18 02:04:41 2019	(r352467)
+++ stable/12/sys/dev/pci/pci_host_generic_acpi.c	Wed Sep 18 06:50:29 2019	(r352468)
@@ -125,7 +125,7 @@ pci_host_generic_acpi_attach(device_t dev)
 	struct generic_pcie_acpi_softc *sc;
 	ACPI_HANDLE handle;
 	ACPI_STATUS status;
-	int error;
+	int error, bus_start;
 
 	sc = device_get_softc(dev);
 
@@ -136,10 +136,14 @@ pci_host_generic_acpi_attach(device_t dev)
 		device_printf(dev, "Bus is%s cache-coherent\n",
 		    sc->base.coherent ? "" : " not");
 
-	if (!ACPI_FAILURE(acpi_GetInteger(handle, "_BBN", &sc->base.ecam)))
-		sc->base.ecam >>= 7;
-	else
+	if (!ACPI_FAILURE(acpi_GetInteger(handle, "_BBN", &bus_start))) {
+		sc->base.ecam = bus_start >> 7;
+		sc->base.bus_start = bus_start & 0x7F;
+	} else {
 		sc->base.ecam = 0;
+		sc->base.bus_start = 0;
+	}
+	sc->base.bus_end = 0xFF;
 
 	acpi_pcib_fetch_prt(dev, &sc->ap_prt);
 
@@ -194,17 +198,12 @@ static int
 generic_pcie_acpi_read_ivar(device_t dev, device_t child, int index,
     uintptr_t *result)
 {
-	ACPI_HANDLE handle;
 	struct generic_pcie_acpi_softc *sc;
-	int secondary_bus;
 
 	sc = device_get_softc(dev);
 
 	if (index == PCIB_IVAR_BUS) {
-		handle = acpi_get_handle(dev);
-		if (ACPI_FAILURE(acpi_GetInteger(handle, "_BBN", &secondary_bus)))
-			secondary_bus = sc->base.ecam * 0x80;
-		*result = secondary_bus;
+		*result = sc->base.ecam * 0x80 + sc->base.bus_start;
 		return (0);
 	}
 

Modified: stable/12/sys/dev/pci/pci_host_generic_fdt.c
==============================================================================
--- stable/12/sys/dev/pci/pci_host_generic_fdt.c	Wed Sep 18 02:04:41 2019	(r352467)
+++ stable/12/sys/dev/pci/pci_host_generic_fdt.c	Wed Sep 18 06:50:29 2019	(r352468)
@@ -152,6 +152,9 @@ pci_host_generic_attach(device_t dev)
 		device_printf(dev, "Bus is%s cache-coherent\n",
 		    sc->base.coherent ? "" : " not");
 
+	/* TODO parse FDT bus ranges */
+	sc->base.bus_start = 0;
+	sc->base.bus_end = 0xFF;
 	error = pci_host_generic_core_attach(dev);
 	if (error != 0)
 		return (error);
@@ -423,6 +426,7 @@ generic_pcie_fdt_activate_resource(device_t dev, devic
 		}
 		break;
 	case SYS_RES_MEMORY:
+	case SYS_RES_IRQ:
 		res = BUS_ACTIVATE_RESOURCE(device_get_parent(dev), child,
 		    type, rid, r);
 		break;
@@ -445,6 +449,7 @@ generic_pcie_fdt_deactivate_resource(device_t dev, dev
 	switch(type) {
 	case SYS_RES_IOPORT:
 	case SYS_RES_MEMORY:
+	case SYS_RES_IRQ:
 		res = BUS_DEACTIVATE_RESOURCE(device_get_parent(dev), child,
 		    type, rid, r);
 		break;



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